HD6417020SX20IV Renesas Electronics America, HD6417020SX20IV Datasheet - Page 340

• Manufacturer Part Number: HD6417020SX20IV
• Description: SH 1 CORE 32B MPU, 20MHZ/5V, 100
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7020r

Specifications of HD6417020SX20IV

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

TPC Output Non-Overlap Operation (Four-Phase Complementary Non-Overlap Output)
(figure 11.7):
1. Set GRA and GRB of the ITU that serves as output trigger in the output compare registers. Set
2. Write H'FFFF in the PBCR1, write H'FF in the NDERB, and set G3CMS1, G3CMS0,
3. When the selected ITU channel starts operating and a GRB compare-match occurs, 1 output
4. Four-phase complementary non-overlap output can be obtained by writing H'59, H'56, H'95…
322 RENESAS
the cycle in the GRB and the non-overlap cycle time in the GRA and select to clear the counter
upon compare match B. Set the IMIEA bit of TIER to 1 to enable the IMIA interrupt.
G2CMS1 and G2CMS0 in the TPCR to set the ITU compare match selected in step 1 as the
output trigger. Set the G3NOV and G2NOV bits in the TPMR to 1 to set the non-overlap
operation. Write output data H'95 in the NDRB.
changes to 0 output; when a GRA compare match occurs, 0 output changes to 1 output. (The
change from 0 output to 1 output is delayed by the value set in GRA.) The IMIA interrupt
service routine writes the next output data (H'65) in the NDRB.
at successive IMIA interrupts. If the DMA controller is set for activation by compare-match,
pulse output can be obtained without loading the CPU.