HD6417020SX20IV Renesas Electronics America, HD6417020SX20IV Datasheet - Page 366

• Manufacturer Part Number: HD6417020SX20IV
• Description: SH 1 CORE 32B MPU, 20MHZ/5V, 100
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7020r

Specifications of HD6417020SX20IV

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Bit 5 (transmit enable (TE)): TE enables or disables the SCI transmitter.
Bit 5: TE
0
1
•
Bit 4: RE
0
1
•
Bit 3: MPIE
0
1
Bit 4 (receive enable (RE)): RE enables or disables the SCI receiver.
Bit 3 (multiprocessor interrupt enable (MPIE)): MPIE enables or disables multiprocessor
interrupts. The MPIE setting is used only in the asynchronous mode, and only if the
multiprocessor mode bit (MP) in the serial mode register (SMR) is set to 1 during reception.
The MPIE setting is ignored in the clocked synchronous mode or when the MP bit is cleared to
0.
Description
Transmitter disabled. The transmit data register empty bit (TDRE) in
the serial status register (SSR) is locked at 1 (initial value).
Transmitter enabled. Serial transmission starts when the transmit data
register empty (TDRE) bit in the serial status register (SSR) is cleared
to 0 after writing of transmit data into the TDR. Select the transmit
format in the SMR before setting TE to 1.
Description
Receiver disabled (initial value). Clearing RE to 0 does not affect the
receive flags (RDRF, FER, PER, ORER). These flags retain their
previous values.
Receiver enabled. Serial reception starts when a start bit is detected in
the asynchronous mode, or serial clock input is detected in the clocked
synchronous mode. Select the receive format in the SMR before
setting RE to 1.
Description
Multiprocessor interrupts are disabled (normal receive operation) (initial
value)
MPE is cleared to 0 when:
1. MPIE is cleared to 0, or
2. Multiprocessor bit (MPB) is set to 1 in receive data.
Multiprocessor interrupts are enabled: Receive-data-full interrupt
requests (RXI), receive-error interrupt requests (ERI), and setting of
the RDRF, FER, and ORER status flags in the serial status register
(SSR) are disabled until the multiprocessor bit is set to 1.
The SCI does not transfer receive data from the RSR to the RDR, does
not detect receive errors, and does not set the RDRF, FER, and ORER
flags in the serial status register (SSR). When it receives data that
includes MPB = 1, MPB is set to 1, and the SCI automatically clears
MPIE to 0, generates RXI and ERI interrupts (if the TIE and RIE bits in
the SCR are set to 1), and allows the FER and ORER to be set.
RENESAS 349