HD6417020SX20IV Renesas Electronics America, HD6417020SX20IV Datasheet - Page 225

• Manufacturer Part Number: HD6417020SX20IV
• Description: SH 1 CORE 32B MPU, 20MHZ/5V, 100
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7020r

Specifications of HD6417020SX20IV

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

• Transfers ending when the NMIF or AE bit is set to 1 in DMAOR: When an NMI interrupt or
• Transfers ending when DME is cleared to 0 in DMAOR: Clearing the DME bit to 0 in the
9.4
9.4.1
In the following example, data is transferred from an on-chip RAM to a memory-mapped external
device with an input capture A/compare match A interrupt (IMIA0) from channel 0 of the 16-bit
integrated-timer pulse unit (ITU) as the transfer request signal. The transfer is performed by
DMAC channel 3. Table 9.7 shows the transfer conditions and register values.
Table 9.7
Transfer Conditions
Transfer source: on-chip RAM
Transfer destination: memory-mapped external device
Number of transfers: 8
Transfer destination address: fixed
Transfer source address: incremented
Transfer request source (transfer request signal): ITU channel
0 (IMIA0)
Bus mode: cycle steal
Transfer unit: byte
DEI interrupt request generated at end of transfer (channel 3
enabled for transfer)
Channel priority order: fixed (0 > 3 > 2 > 1) (all channels
transfer enabled)
206 RENESAS
DMAC address error occurs, the NMIF or AE bit is set to 1 in the DMAOR and all channels
stop their transfers. The SAR, DAR, TCR are all updated by the transfer immediately
preceding the halt. The TE bit is not set. To resume the transfers after NMI interrupt exception
processing or address error exception processing, clear the appropriate flag bit to 0. When a
channel’s DE bit is then set to 1, the transfer on that channel will restart. To avoid restarting a
transfer on a particular channel, keep its DE bit cleared to 0. In the dual address mode, the
DMA transfer will be halted after the completion of the write cycle that follows the initial read
cycle in which the address error occurs. SAR, DAR and TCR are updated by the final transfer.
DMAOR forcibly aborts the transfers on all channels at the end of the current cycle. The TE
bit is not set.
Examples of Use
DMA Transfer between On-Chip RAM and a Memory-Mapped External Device
Transfer Conditions and Register Settings for Transfer Between On-Chip RAM
and Memory-Mapped External Device
Register
SAR3
DAR3
TCR3
CHCR3
DMAOR
Setting
H'FFFFE00
Destination address
H'0008
H'1805
H'0001