HD6417020SX20IV Renesas Electronics America, HD6417020SX20IV Datasheet - Page 183

SH 1 CORE 32B MPU, 20MHZ/5V, 100

HD6417020SX20IV

Manufacturer Part Number
HD6417020SX20IV
Description
SH 1 CORE 32B MPU, 20MHZ/5V, 100
Manufacturer
Renesas Electronics America
Series
SuperH® SH7020r
Datasheet

Specifications of HD6417020SX20IV

Core Processor
SH-1
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Type
ROMless
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
For the signal output shown by solid lines, DRAM data may not be held. Therefore, when DRAM
data must be held after reset, take one of the coutermeasures described as follows.
1. When resetting manually, do this in watchdog timer (WDT) condition.
2. Even if the Low width of RAS becomes as short as 1.5 tcyc as shown above, use with a
3. Even in case the Low width of RAS has become 1.5 tcyc, proceed by using the external circuit
A0 to A21
A0 to A21
frequency that satisfies the DRAM standard (tRAS).
so that a RAS signal with a Low width of 2.5 tcyc is input in the DRAM (in case the Low
width of RAS is higher than 2.5 tcyc, operate so that the current waveform is input in the
DRAM).
RES
RAS
CAS
RES
RAS
CAS
RD
CK
CK
RD
RES latch
timing
RES latch
Figure 8.40 Long - pitch Mode Read (1)
Figure 8.41 Long - pitch Mode Read (2)
timing
Manual reset
Manual reset
Tp
Tp
Row address
Row address
Tr
Tr
Colum address
FFFF
Tc1
Tc1
FFFF
Tc2
Tc2
RENESAS 163

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