HD6417020SX20IV Renesas Electronics America, HD6417020SX20IV Datasheet - Page 252

• Manufacturer Part Number: HD6417020SX20IV
• Description: SH 1 CORE 32B MPU, 20MHZ/5V, 100
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7020r

Specifications of HD6417020SX20IV

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

General registers are connected to the CPU by a 16-bit bus, so general registers can be written or
read by either word access or byte access. General registers are initialized to the output compare
register (no pin output) by a reset or in standby mode. The initial value is H'FFFF.
Table 10.5 General Registers A and B (GRA and GRB)
Channel
0
1
2
3
4
10.2.8
Each buffer register is a 16-bit read/write register that is used in the buffer mode. The ITU has
four buffer registers, two each for channels 3 and 4 (table 10.6). Buffer operation can be set
independently by the timer function control register (TFCR) bits BFB4, BFA4, BFB3, and BFB3
bits. The buffer registers are paired with the general registers and their function changes
automatically to match the function of its corresponding general register.
The buffer registers are connected to the CPU by a 16-bit bus, so they can be written or read by
either word or byte access. Buffer registers are initialized to H'FFFF by a reset or in standby mode.
234 RENESAS
Initial value:
Initial value:
Bit name:
Bit name:
Buffer Registers A and B (BRA, BRB)
Abbreviation
GRA0, GRB0
GRA1, GRB1
GRA2, GRB2
GRA3, GRB3
GRA4, GRB4
R/W:
R/W:
Bit:
Bit:
R/W
R/W
15
1
7
1
Function
Output compare/input capture dual register
Output compare/input capture dual register. Can also be set for
buffer operation in combination with the buffer registers (BRA, BRB)
R/W
R/W
14
1
6
1
R/W
R/W
13
1
5
1
R/W
R/W
12
1
4
1
R/W
R/W
11
1
3
1
R/W
R/W
10
1
2
1
R/W
R/W
9
1
1
1
R/W
R/W
8
1
0
1