HD6417020SX20IV Renesas Electronics America, HD6417020SX20IV Datasheet - Page 136

• Manufacturer Part Number: HD6417020SX20IV
• Description: SH 1 CORE 32B MPU, 20MHZ/5V, 100
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7020r

Specifications of HD6417020SX20IV

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Table 8.6
Area Address
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
Notes: 1. When MD2–MD0 pins are 010
116 RENESAS
H'0000000 – H'0FFFFFF On-chip ROM*
H'1000000 – H'1FFFFFF External memory
H'2000000 – H'2FFFFFF External memory
H'3000000 – H'3FFFFFF External memory
H'4000000 – H'4FFFFFF External memory
H'5000000 – H'5FFFFFF On-chip peripheral module 512 B
H'6000000 – H'6FFFFFF External memory*
H'7000000 – H'7FFFFFF External memory
H'8000000 – H'8FFFFFF On-chip ROM*
H'9000000 – H'9FFFFFF External memory
H'A000000 – H'AFFFFFF External memory
H'B000000 – H'BFFFFFF External memory
H'C000000 – H'CFFFFFF External memory
H'D000000 – H'DFFFFFF External memory
H'E000000 – H'EFFFFFF External memory
H'F000000 – H'FFFFFFF On-chip RAM
2. When MD2–MD0 pins are 000 or 001
3. For SH7020
4. For SH7021
5. Select with MD0 pin
6. Select with DRAME bit in BCR
7. Divided into 8-bit and 16-bit space according to value of address bit A8 (Long word
8. Divided into 8-bit space and 16-bit space by value of address bit A14
9. Select with IOE bit of BCR
accesses are inhibited, however, in on-chip peripheral modules with bus widths of 8
bits. Some on-chip peripheral modules with bus widths of 16 bits also have registers
that are only byte-accessible and registers for which byte access is inhibited. For
details, see the sections on the individual modules.)
How Space is Divided
Assign-able Memory
External memory*
DRAM*
Multiplexed I/O
External memory*
DRAM*
6
6
1
1
2
9
2
Capacity
(linear space)
16 kB*
32 kB*
4 MB
4 MB
16 MB
4 MB
4 MB
4 MB
4 MB
4 MB
4 MB
16 kB*
32 kB*
4 MB
4 MB
16 MB
4 MB
4 MB
4 MB
4 MB
4 MB
1 kB
3
4
3
4
Bus
Width
32
8/16*
8
8
8
8
8
8/16*
8/16*
8
32
8/16*
16
16
16
16
16
16
16
32
5
7
8
5
CS
Output
—
CS0
CS1
RAS CAS
CS2
CS3
CS4
—
CS6
CS7
—
CS0
CS1
RAS CAS
CS2
CS3
CS4
CS5
CS6
—