HD6417020SX20IV Renesas Electronics America, HD6417020SX20IV Datasheet - Page 184

• Manufacturer Part Number: HD6417020SX20IV
• Description: SH 1 CORE 32B MPU, 20MHZ/5V, 100
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7020r

Specifications of HD6417020SX20IV

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

The countermeasures are not required when DRAM data is initialized or loaded again after manual
reset.
8.11.2
The following specifies the setup time tDS of the parity dada DPH and DPL to CAS signal rising
when the parity dada DPH and DPL are written to DRAM in long-pitch mode (early write).
Table 8.12 Setup Time of Parity Data DPH and DPL
(for only DPH and DPL in long-pitch mode)
Therefore, when writing parity data DPH and DPL to the DRAM in long-pitch mode, delay the
WRH and WRL signals of this LSI and write with delayed writing.
Nomal dada is also delayed-written, causing no problems.
8.11.3
The maximum number of states from BREQ input to bus release is:
Note: Breakdown of approx. 4.5 states:
164 RENESAS
Data setup time to CAS
Microcomputer
Maximum number of states for which bus is not released + approx. 4.5 states
SuperH
1.5 states:
1 state (min.):
1 state (max.):
1 state:
WRH or WRL
Usage Notes on Parity Data Pins DPH and DPL
Maximum Number of States from BREQ Input to Bus Release
RAS
CAS
RD
CK
Figure 8.42 Delayed-Write Control Circuit
Until BACK output after end of bus cycle
tBACD1
tBRQS
Sampling in 1 state before end of bus cycle
Item
*1
*1
D
*2
Q
Q
DWRH or DWRL
*1: For preventing signal racing
*2: Negative edge latch
Symbol
tDS
RAS
CAS
OE
WE
DRAM
–5 ns
min