HD6417020SX20IV Renesas Electronics America, HD6417020SX20IV Datasheet - Page 248

• Manufacturer Part Number: HD6417020SX20IV
• Description: SH 1 CORE 32B MPU, 20MHZ/5V, 100
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7020r

Specifications of HD6417020SX20IV

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

10.2.4
The timer function control register (TFCR) is an 8-bit read/write register that selects
complementary PWM/reset-synchronized PWM for channels 3 and 4 and sets the buffer operation.
TFCR is initialized on a reset or standby mode to H'C0 or H'40.
Note: Undefined
• Bits 7 and 6 (reserved): Bit 7 is read as undefined. Bit 6 is always read as 1. The write value to
• Bits 5 and 4 (combination mode 1 and 0 (CMD1 and CMD0)): CMD1 and CMD0 select the
Bit 5: CMD1
0
1
• Bit 3 (buffer mode B4 (BFB4)): BFB4 selects the buffer mode for GRB4 and BRB4 in channel
Bit 3: BFB4
0
1
230 RENESAS
bit 7 should be 0 or 1. The write value to bit 6 should always be 1.
complementary PWM mode or reset-synchronized mode for channels 3 and 4. Set the
complementary PWM/reset-synchronized PWM mode while the timer counter (TCNT) being
used is off. When these bits are used to set the complementary PWM/reset-synchronized PWM
mode, they take priority over the PWM4 and PWM3 bits of the TMDR. While the
complementary PWM/reset-synchronized PWM mode settings and the SYNC4 and SYNC3 bit
settings of the timer synchro register (TSNC) are valid simultaneously, when the
complementary PWM mode is set, channels 3 and 4 should not be set to operate
simultaneously (SYNC 4 and SYNC 3 bits of TSNC should not both be set to 1).
4.
Initial value:
Bit name:
Timer Function Control Register (TFCR)
R/W:
Bit:
Bit 4: CMD0
0
1
0
1
—
—
7
*
Description
GRB4 operates normally in channel 4 (initial value)
GRB4 and BRB4 operate in buffer mode in channel 4
—
—
6
1
Description
Channels 3 and 4 operate normally (initial value)
Channels 3 and 4 operate normally
Channels 3 and 4 operate together in complementary PWM
mode
Channels 3 and 4 operate together in reset-synchronized
PWM mode
CMD1
R/W
5
0
CMD0
R/W
4
0
BFB4
R/W
3
0
BFA4
R/W
2
0
BFB3
R/W
1
0
BFA3
R/W
0
0