HD6417020SX20IV Renesas Electronics America, HD6417020SX20IV Datasheet - Page 231

• Manufacturer Part Number: HD6417020SX20IV
• Description: SH 1 CORE 32B MPU, 20MHZ/5V, 100
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7020r

Specifications of HD6417020SX20IV

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

10.1
The SuperH microcomputer has an on-chip 16-bit integrated-timer pulse unit (ITU) with five
channels of 16-bit timers.
10.1.1
ITU features are listed below:
•
•
•
•
•
•
•
•
Can process a maximum of twelve different pulse outputs and ten different pulse inputs.
Has ten general registers (GR), two per channel, that can be set to function independently as
output compare or input capture.
Selection of eight counter input clock sources for all channels
All channels can be set for the following operating modes:
Channel 2 can be set to the phase counting mode: Two-phase encoder output can be counted
automatically.
Channels 3 and 4 can be set in the following modes:
Buffer operation: Input capture registers can be double-buffered. Output compare registers can
be updated automatically.
High-speed access via internal 16-bit bus: The TCNT, GR, and buffer register (BR) 16-bit
registers can be accessed at high speed via a 16-bit bus.
Section 10 16-Bit Integrated-Timer Pulse Unit (ITU)
Internal clock: , /2, /4, /8,
External clock: TCLKA, TCLKB, TCLKC, TCLKD
Compare match waveform output: 0 output/1 output/selectable toggle output (0 output/1
Input capture function: Selectable rising edge, falling edge, or both rising and falling edges.
Counter clearing function: Counters can be cleared by a compare match or input capture.
Synchronizing mode: Two or more timer counters (TCNT) can be written to
PWM mode: PWM output can be provided with any duty cycle. When combined with the
Reset-synchronized PWM mode: By combining channels 3 and 4, 3-phase PWM output is
Complementary PWM mode: By combining channels 3 and 4, 3-phase PWM output is
output for channel 2).
simultaneously. Two or more timer counters can be simultaneously cleared by a compare
match or input capture. Counter synchronization functions enable synchronized
input/output.
counter synchronizing function, enables up to five-phase PWM output.
possible with positive and negative waveforms .
possible with non-overlapping positive and negative waveforms.
Overview
Features
RENESAS 213