HD6417020SX20IV Renesas Electronics America, HD6417020SX20IV Datasheet - Page 165

• Manufacturer Part Number: HD6417020SX20IV
• Description: SH 1 CORE 32B MPU, 20MHZ/5V, 100
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7020r

Specifications of HD6417020SX20IV

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

• Long-pitch, high-speed page mode: When the RW1, WW1, DRW1, and DWW1 bits in WCR1
Figure 8.25 Short Pitch High-Speed Page Mode (When read and write cycle continues with
AD15–
Note: Access A and B are examples of 32-bit data accesses in their respective 16-bit bus width
The high-level duty of the CAS signal can be selected in the short pitch high-speed page mode
using the CAS duty bit (CDTY) in the DCR. When the CDTY bit is cleared to 0, high-level
duty is 50% of the TC state; when CDTY is set to 1, it is 35% of the T
and WCR2 are set to 1, and the corresponding DRAM access cycle is continuing, the CAS
signal and column address output cycles (2 states) continue as long as the row addresses
continue to match. When the WAIT signal is detected at the low level, the second cycle of the
column address output cycle is repeated as the wait state. Figure 8.26 shows the timing for the
long pitch high-speed page mode. See section 20.3.3, Bus Timing, for more information about
the timing.
A21–
RAS
CAS
AD0
WR
CK
A0
spaces.
T
p
Row address
Access A (read)
T
address A-1
r
Column
Read data A-1 Read data A-2 Write data B-1 Write data B-2
the same row address)
T
c
address A-2
Column
T
c
Silent
cycle
address B-1
Access B (write)
Column
T
c
C
state.
address B-2
Column
T
c
RENESAS 145