PNX1501E NXP Semiconductors, PNX1501E Datasheet - Page 264

• Manufacturer Part Number: PNX1501E
• Description: Digital Signal Processors & Controllers (DSP, DSC) MEDIA PROCESSOR PNX15XX/266MHZ
• Manufacturer: NXP Semiconductors

Specifications of PNX1501E

• Product: DSPs
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-795
• Minimum Operating Temperature: 0 C
• Lead Free Status / Rohs Status: Details
• Other names: PNX1501E,557

Philips Semiconductors
Volume 1 of 1
12NC 9397 750 14321
Product data sheet
Figure 2:
ANY
MODULE
Functional Block Diagram of a GPIO Pin
2.1.1 GPIO Mode settings
2.1.2 GPIO Data Settings MMIO Registers
MODULE
FUNCTIONAL
OUTPUT
MODULE
FUNCTIONAL
INPUT
MODULE
FUNCTIONAL
OUTPUTE ENABLE
(OEN)
The GPIO pins are controlled by software through MMIO register reads and writes.
The MMIO registers allow to control the operating mode of the GPIO pin (on a pin-by-
pin basis) but also set its value or read its value.
Each GPIO pin operates in 1 of 3 following modes:
There are four GPIO Mode Control registers allocated to control the operating mode
of the 61 PNX15xx Series GPIO pins. Each pin uses a 2-bit mode field located in one
of the 4 Mode Control registers. Register MC0 controls GPIO pins [15:0], MC1
controls pins [31:16], etc. The 2-bit control values function is described in
The complete MMIO register layouts are in
Table 2: GPIO Mode Select
When a pin is set for GPIO mode, the data can be read and written by accessing one
of four MASK and I/O Data (IOD) registers. Each of these registers accesses 16 of
the 61 GPIO signals. Each register is composed of 16 MASK bits and 16 IOD bits.
The MASK and IOD field make up a 2-bit value: the MASK bit is located in the upper
16 bits (31:16) and the IOD bit is located in the lower 16 bits (15:0) of the
corresponding 32-bit MMIO register (groups 16 GPIO pins). For example, MASK
GPIO
Mode
00
01
10
11
•
•
•
primary function
open drain output
tri-state output.
Description
Retain pin mode of operation. A write with this mode does not overwrite current
mode.
Switch pin mode to primary operating mode.
Switch pin mode to GPIO mode.
Switch pin mode to open-drain GPIO (this prevents active high drive).
Rev. 2 — 1 December 2004
Disabling
Logic
GPIO
GPIO
Logic
GPIO
Muxing
Chapter 8: General Purpose Input Output Pins
Section
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
PAD INPUT
PAD OUTPUT
4.1.
PNX15xx Series
OEN
Table
PIN
2.
8-4