PNX1501E NXP Semiconductors, PNX1501E Datasheet - Page 422

• Manufacturer Part Number: PNX1501E
• Description: Digital Signal Processors & Controllers (DSP, DSC) MEDIA PROCESSOR PNX15XX/266MHZ
• Manufacturer: NXP Semiconductors

Specifications of PNX1501E

• Product: DSPs
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-795
• Minimum Operating Temperature: 0 C
• Lead Free Status / Rohs Status: Details
• Other names: PNX1501E,557

Philips Semiconductors
Volume 1 of 1
2. Functional Description
Table 1: VIP Submodule Descriptions
12NC 9397 750 14321
Product data sheet
Submodule
Test Pattern
Video Timing
Control
Video Extract
Brief Description of Functionality
An internal generator that produces 4:2:2 NTSC/PAL video streams
This submodule receives incoming data samples from either the Test Pattern Generator or the Digital
Video Port.
A tally of the sample is maintained when it conforms to the ITU-R 656 or ITU-R 1364.
Video and Aux samples are forwarded to Video Extract and Aux Data Extract respectively.
Video input pipe windower. This submodule:
receives video samples from Video Port Input module.
captures desired samples in a programmable size rectangular area (window).
forwards captured samples to the Pre-Dither unit.
2.1 VIP Block Level Diagram
The main functional blocks of the VIP and the primary data paths (not including syncs
etc.) are shown in
A brief description of each of the submodules is given in
Figure 1:
•
•
•
•
•
•
–
Allows color-space conversion (mutually exclusive with scaling) on the video
path.
Allows 4:2:2 to 4:4:4 conversions on the video path.
Provides last-pixel-in signals, for VBI and video data, to the GPIO block for
Timestamping.
Features interrupt generation, for VBI or video data written to memory.
Provides an internal Test Pattern Generator with NTSC, PAL, and variable format
support.
Features a wide variety of output formats such as planar YUV 4:4:4, planar YUV
4:2:2, planar RGB, semi-planar YUV 4:2:2 packed UYVY, etc. Planar formats are
mutually exclusive with the VBI capture.
Input
ports
Permits optional linear phase interpolation / nonlinear phase interpolation (as
in MBS).
Pattern
Test
Simplified VIP Block Diagram
10
10
Rev. 2 — 1 December 2004
10
Figure
Control
Extract
Timing
Video
10
Video
1.
10
16
10
10
Post-Dither
Pre-Dither
AUX Data
Extract
and
8
8
Sample
Chapter 12: Video Input Processor
Up
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
8
8
8
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Table
Horizontal
PNX15xx Series
Phase
Poly
FIR
1.
8
8
8
write DMA
3 channel
Sample
Down
control
8
PSU
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8
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