PNX1501E NXP Semiconductors, PNX1501E Datasheet - Page 270

• Manufacturer Part Number: PNX1501E
• Description: Digital Signal Processors & Controllers (DSP, DSC) MEDIA PROCESSOR PNX15XX/266MHZ
• Manufacturer: NXP Semiconductors

Specifications of PNX1501E

• Product: DSPs
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-795
• Minimum Operating Temperature: 0 C
• Lead Free Status / Rohs Status: Details
• Other names: PNX1501E,557

Philips Semiconductors
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Product data sheet
The length of the interval duration is programmed using the
GPIO_EV[3:0].INTERVAL fields.
Remark: If there is no internal buffer data to be flushed and no valid data in the DMA
buffers the interval of silence will not cause BUFx_RDY to be asserted.
Remark: timestamping always works, even if the pin selected for monitoring is
operating in its functional mode.
More About the Sampling Mode
In ‘signal sampling’ a signal,
programmed frequency or by a selected clock input.
The programmed sampling frequency is divided down from 108 MHz using a 16-bit
divider. The sampling frequency is programmed in the DIVIDER[3:0].FREQ_DIV
fields. The generated clock has a 50% duty cycle if the divider is an even number. In
the case of an odd value the duty cycle is 33-66 or 66-33.
Instead of using the internal 108 MHz sampling clock it is possible to use one of the
GPIO[6:0] inputs as the sampling clock. This is enabled using the bit fields
EN_CLOCK_SEL and CLOCK_SEL in the GPIO_EV[3:0] registers. Some of the
GPIO[6:0] pins can receive a clock coming from a PNX15xx Series DDS clock
generators, see
clocks need to be turned on by programming the clock module, refer to
Clock
Signal sampling, should be done with a clock that is at least twice the signal
frequency.
The input signals to sample can be grouped together and sampled at once in the
same FIFO queue. It is possible to sample 1, 2 or 4 GPIO inputs in one FIFO queue.
The sampled 1, 2 or 4 bits fill a 32-bit word full of 32, 16 or 8 samples as pictured in
Figure
Figure 4:
Module. Alternately the clocks can be generated at board level.
5. The resulting 32-bit word of the sampled signals is written to the DMA
1-bit Signal Sampling
Monitored
Signal
Clock
Section
Rev. 2 — 1 December 2004
Programmed Frequency
2.5. If this feature is used it is important to know that these
Sample: 0110....100
Figure
0
Chapter 8: General Purpose Input Output Pins
4, or a group of signals can be monitored at a
1
2
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
Write 32-bits to DMA buffer
...
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PNX15xx Series
31
Chapter 5 The
8-10