PNX1501E NXP Semiconductors, PNX1501E Datasheet - Page 382

• Manufacturer Part Number: PNX1501E
• Description: Digital Signal Processors & Controllers (DSP, DSC) MEDIA PROCESSOR PNX15XX/266MHZ
• Manufacturer: NXP Semiconductors

Specifications of PNX1501E

• Product: DSPs
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-795
• Minimum Operating Temperature: 0 C
• Lead Free Status / Rohs Status: Details
• Other names: PNX1501E,557

Philips Semiconductors
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Product data sheet
3.4.1 Changing Timing
3.5 Programming QVCP for Different Output Formats
The QVCP provides clipping support at the edge of the defined H- and V-total. If a
layer is positioned in a way that some part of it would exceed the overall screen
dimensions, no wrapping occurs but the pixel layering in this area is marked as
invalid, hence they are not being displayed.
The QVCP also supports negative screen positions i.e., top and left side clipping of
layers. For negative x and y layer start positions, the following equations must be
used:
if StartX < 0 then
StartX = Xtotal + 1 - ABS(StartX)
set StartX sign bit
StartY = Ydisplay - 1
else
StartX = StartX
StartY = StartY
if StartY < 0 then
StartY = Ytotal + 1 - ABS(StartY)
set StartY sign bit
else
StartY = StartY
In addition to the standard progressive QVCP display mode, another mode called
“interlaced” can be switched on by setting the Interlaced control bit. In this mode the
VTotal register no longer specifies the height of a frame but the height of a field. The
field height alternates by one line depending on whether an odd or even field needs to
be processed by the QVCP. Four registers are provided for this mode to specify the
actual location of the vsync signal within a line in odd and even fields.
All register settings to the timing generator take effect immediately and are not clock
re- synchronized. (The start/stop bit is the exception. It takes effect immediately and
is clock re-synchronized.) The only safe way to change screen timing is as follows:
Table 12
programming bits reside in the “Control” register (offset 0x03C).
1. Turn off the timing generator.
2. Program all registers needed in the new display mode.
3. Turn the timing generator back on. In the process, the entire display pipeline is
reset. All display layers are reset, and the screen timing starts at the vertical total,
which guarantees a complete vertical blank period and vertical sync signal at the
start of any mode change.
shows the programmer how to obtain the desired output formats. The
Rev. 2 — 1 December 2004
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
PNX15xx Series
Chapter 11: QVCP
11-36