PNX1501E NXP Semiconductors, PNX1501E Datasheet - Page 474

• Manufacturer Part Number: PNX1501E
• Description: Digital Signal Processors & Controllers (DSP, DSC) MEDIA PROCESSOR PNX15XX/266MHZ
• Manufacturer: NXP Semiconductors

Specifications of PNX1501E

• Product: DSPs
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-795
• Minimum Operating Temperature: 0 C
• Lead Free Status / Rohs Status: Details
• Other names: PNX1501E,557

Philips Semiconductors
Volume 1 of 1
Table 3: Fast general purpose output (FGPO)
12NC 9397 750 14321
Product data sheet
Bit
1:0
Offset 0x07,1018
31:24
23:0
Offset 0x07,101C
31:24
23:0
Offset 0x07,1020
31:24
23:0
Offset 0x07,1024
31:24
23:0
Offset 0x07,1028
31:24
23:0
Offset 0x07,102C
31:24
23:0
Offset 0x07,1030
31:0
Offset 0x07,1034
31:0
Symbol
Reserved
Reserved
NREC1
Reserved
NREC2
Reserved
THRESH1
Reserved
THRESH2
Reserved
REC_GAP
Reserved
BUF_GAP
TIME1
TIME2
4.2 Status Registers
FGPO_NREC1
FGPO_NREC2
FGPO_THRESH1
FGPO_THRESH2
FGPO_REC_GAP
FGPO_BUF_GAP
FGPO_TIME1
FGPO_TIME2
Acces
s
R
R
R
R
R
R
R/W
R
R/W
R
R/W
R
R/W
R
R
Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
…Continued
Rev. 2 — 1 December 2004
Description
Always 0.
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
Number of records/messages output from buffer 1.
Cleared to zero when FGPO_BASE1 register is written to.
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
Number of records/messages output from buffer 2.
Cleared to zero when FGPO_BASE1 register is written to.
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
THRESH1_REACHED interrupt generated when FGPO_NREC1
count equals this register value. Range: 1 to 2
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
THRESH2_REACHED interrupt generated when FGPO_NREC2
count equals this register value. Range: 1 to 2
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
Clock delay after a record/message is output before the next record/
message is output. Range: 1 to 2
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
Clock delay after a buffer is output before the next buffer is output.
Range: 1 to 2
Holds timestamp when buffer 1 completed.
Holds timestamp when buffer 2 completed.
Chapter 13: FGPO: Fast General Purpose Output
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© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
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