PNX1501E NXP Semiconductors, PNX1501E Datasheet - Page 434

• Manufacturer Part Number: PNX1501E
• Description: Digital Signal Processors & Controllers (DSP, DSC) MEDIA PROCESSOR PNX15XX/266MHZ
• Manufacturer: NXP Semiconductors

Specifications of PNX1501E

• Product: DSPs
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-795
• Minimum Operating Temperature: 0 C
• Lead Free Status / Rohs Status: Details
• Other names: PNX1501E,557

Philips Semiconductors
Volume 1 of 1
12NC 9397 750 14321
Product data sheet
Figure 11: Double Buffer Mode
dma_base1
dma_base2
Capture Enable Mode
Using the cfen bits, video capture can be limited to odd or even or both fields. If both
fields are to be captured, the capture starts with the next odd field.
The status of the
mode (one-shot or continuous):
Programming hint: In a video conference application the captured image would be a
one-shot stream to the host memory. If you write
register, it is captured on the next VSYNC and
the next image, the
Address Generation
The line address is generated by loading the base address from the corresponding
register set at the beginning of each field and adding the line pitch to it at the
beginning of every new line.The lower three bits of the first three base address
registers are used as an intra-long-word offset for the left-most pixel components of
each line. The offset has to be a multiple of the number of bytes per component.
Double Buffer Mode
To avoid line tear caused by trying to display a frame at the same time that it is being
updated, a double buffer mode is available. In this double buffer mode, a second set
of DMA base addresses is available. After capturing and storing one complete frame
in the location described by one set, the other set is used for the next frame. The idea
is illustrated in
•
•
If osm=0, the corresponding incoming video stream is captured continuously. For
example, in a video conference application the vanity image would be a
continuous stream to the frame buffer.
If osm=1, the corresponding incoming video stream is captured one field or frame
at a time (depending on the cfen bits).
Frame 1
Figure
Even
Odd
osm
Rev. 2 — 1 December 2004
cfen and osm
(one-shot) bit in the mode-control-register specifies the capture
11.
dma_base3
dma_base4
bits must be reprogrammed.
Frame 2
cfen
Chapter 12: Video Input Processor
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
Even
Odd
osm
bits are cleared to 0. To capture
=1 and select field/frame in the
PNX15xx Series
12-14