PNX1501E NXP Semiconductors, PNX1501E Datasheet - Page 525

• Manufacturer Part Number: PNX1501E
• Description: Digital Signal Processors & Controllers (DSP, DSC) MEDIA PROCESSOR PNX15XX/266MHZ
• Manufacturer: NXP Semiconductors

Specifications of PNX1501E

• Product: DSPs
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-795
• Minimum Operating Temperature: 0 C
• Lead Free Status / Rohs Status: Details
• Other names: PNX1501E,557

Philips Semiconductors
Volume 1 of 1
12NC 9397 750 14321
Product data sheet
3.2 Reset-Related Issues
If set as output, WS can similarly be programmed using WSDIV to control the serial
frame length from 1 to 512 bits. The number of bits per frame is equal to WSDIV + 1.
Table 2
achieve a bit clock of 64 f
Table 2: Sample Rate Settings
The preferred application of the clock system options is to use OSCLK as A/D master
clock, and let the A/D converter be timing master over the serial interface
(SER_MASTER = 0).
In case of an external codec for common audio input and audio output use, it may not
be possible to independently control the A/D and D/A system clocks. It is
recommended that the Audio Out clock system DDS is used to provide a single
master A/D and D/A clock. The Audio Out or the D/A converter can be used as serial
interface timing master, and Audio In is set to be slave to the serial frame determined
by Audio Out (Audio In SER_MASTER = 0, SCK and WS externally wired to the
corresponding Audio Out pins). In such systems, independent software control over
A/D and D/A sampling rate is not possible, but component count is minimized.
The Audio In unit is reset by a chip level hardware reset or by writing logic ‘1’ to the
AI_CTL.RESET register bit. As soon as the software reset bit is written, further MMIO
commands are held off until the software reset has taken effect in the IP clock domain
and the reset state restored. Upon RESET, capture is disabled (CAP_ENABLE = 0),
and buffer1 is the active buffer (BUF1_ACTIVE = 1).
If the Audio In module was operating in clock master mode (SER_MASTER = 1) then
a reset action prevents the SCK clock to be generated. This prevents the reset to
complete. Therefore upon a software reset the AI module clock must be switched to
the default 27 MHz (crystal input) in order to complete the reset.
Software should follow a series of steps to ensure that Software Reset happens
correctly:
1. Check to see if there is a valid clock present on the Audio Input external clock
input.
2. If there is no clock, then write to the Clocks block to switch the Audio Input clock to
the 27 MHz oscillator.
3. Apply Software Reset and poll the RESET bit until it is cleared.
4. Program the Clocks block to switch the Audio Input external clock back to the
external clock mode.
f
44.1 kHz
48.0 kHz
44.1 kHz
48.0 kHz
s
presents several sample rates with the appropriate SCKDIV necessary to
Rev. 2 — 1 December 2004
s
.
OSCLK
256 f
256 f
384 f
384 f
s
s
s
s
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
SCKDIV
3
3
5
5
PNX15xx Series
Chapter 16: Audio Input
SCK
64 f
64 f
64 f
64 f
s
s
s
s
16-6