PNX1501E NXP Semiconductors, PNX1501E Datasheet - Page 83

• Manufacturer Part Number: PNX1501E
• Description: Digital Signal Processors & Controllers (DSP, DSC) MEDIA PROCESSOR PNX15XX/266MHZ
• Manufacturer: NXP Semiconductors

Specifications of PNX1501E

• Product: DSPs
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-795
• Minimum Operating Temperature: 0 C
• Lead Free Status / Rohs Status: Details
• Other names: PNX1501E,557

Philips Semiconductors
Volume 1 of 1
4. System Memory
Table 3: Footprints for 32-bit and 16-bit DDR Interface
12NC 9397 750 14321
Product data sheet
Total DRAM size
8 MB
16 MB
32 MB
64 MB
128 MB
256 MB
Devices for 32-bit I/F
1 device of 2M x 32 (64 Mbits)
2 devices of 4M x 16 (64 Mbits)
1 device of 4M x 32 (128 Mbits)
2 devices of 8M x 16 (128 Mbits)
1 device of 8M x 32 (256 Mbits)
2 devices of 16M x 16 (256 Mbits)
1 device of 16M x 32 (512 Mbits)
2 devices of 32M x 16 (512 Mbits)
4 devices of 64M x 8 (512 Mbits) 1 rank
4 devices of 32M x 16 (512 Mbits) 2 ranks
4.1 MMI - Main Memory Interface
4.2 Flash
PNX15xx Series has an unified memory system for the PNX15xx Series CPU and all
of its modules. This memory is also visible from any PCI master as PCI attached
memory.
The 32-bit DDR SDRAM interface can operate up to 200 MHz. This is equivalent to a
64-bit SDR SDRAM interface running at 200 MHz, resulting in theoretical available
bandwidth of up to 1.6 GB/s.
This interface can support memory footprints from 8 up to 256 MB. The supported
memory configurations are displayed in
The memory interface also performs the arbitration of the internal memory bus,
guaranteeing adequate bandwidth and latency to the TM3260 CPU, DMA devices
and other internal resources that require memory access. A programmable list-based
memory arbitration scheme is used to customize the memory bandwidth usage of
various hardware modules for a given application. The CPU in the system is given the
ability to intersect long DMA transfers, up to a programmable number of times per
interval. This allows optimal CPU performance at high DDR DMA utilization rate, and
guarantees the real-time needs of audio/video DMA modules.
The memory controller supports most, if not all, DDR SDRAM devices thanks to
programmable memory timing parameters. For example CAS latency, T
and many others can be programmed after the default boot initialization.
NAND and NOR type flash memory connects to the PNX15xx Series by sharing
some PCI bus pins. The XIO bus created by this pin-sharing supports 8- and 16-bit
data peripherals, and uses a few side-band control signals. Refer to
on page 2-24
for more details.
Rev. 2 — 1 December 2004
Devices for 16-bit I/F
1 device of 4M x 16 (64 Mbits)
1 device of 8M x 16 (128 Mbits)
1 device of 16M x 16 (256 Mbits)
1 device of 32M x 16 (512 Mbits)
n/a
n/a
Table
3.
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
PNX15xx Series
Chapter 2: Overview
Section 10.3.2
RC
, T
RAS
, T
RP
2-9