PNX1501E NXP Semiconductors, PNX1501E Datasheet - Page 558

• Manufacturer Part Number: PNX1501E
• Description: Digital Signal Processors & Controllers (DSP, DSC) MEDIA PROCESSOR PNX15XX/266MHZ
• Manufacturer: NXP Semiconductors

Specifications of PNX1501E

• Product: DSPs
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-795
• Minimum Operating Temperature: 0 C
• Lead Free Status / Rohs Status: Details
• Other names: PNX1501E,557

Philips Semiconductors
Volume 1 of 1
12NC 9397 750 14321
Product data sheet
3.2.5 SPDI_CTL and Functions
stream is not present or is suddenly removed, and 3) the input signal contains too
much jitter. If the UNLOCK_ENBL bit is set, the SPDIF Input will generate an
interrupt. Note that parity and validity errors (PERR and VERR) do not cause out of
lock conditions.
From the point where the error condition occurred, the contents of the currently filling
internal 64 byte buffers are muted (zeroed). The external memory buffers will receive
muted data from this point forward. If the receiver does not re-lock before the current
external memory buffer is filled to completion with muted data, DMA will halt. DMA is
halted in this way so that bus resources are not further utilized. Otherwise, DMA
continues with valid data soon after lock is reacquired. From the error point onward,
the last stable capture sample rate will be maintained by the hardware automatically
during this error condition processing. The following is a start-up software process
flow for capture of an SPDIF stream.
The SPDI_CTL register provides system control of the SPDIF Input interface. The
RESET bit is used to completely reset the interface and all registers. The result of
asserting the RESET bit is all SPDIF Input capture activity stops and all registers are
initialized to logic ‘0’s. In addition, any pending SPDIF Input interrupts are cleared and
disabled. Any pending DMA activity is cancelled and active request are aborted.
Figure 7:
Power
on/HW
reset/SW
reset
Lock/Unlock Processing for SPDIF Input
Rev. 2 — 1 December 2004
•
•
•
•
•
•
•
Configure SPDIF Input regis-
ters as necessary.
Enable LOCK interrupt
Disable UNLOCK interrupt
Service LOCK interrupt
Disable LOCK interrupt
Enable UNLOCK interrupt
Enable capture
UNLOCK
indicator auto
asserted by
receiver
processing
UNLOCK
indicator
indicator
Normal
active?
active?
LOCK
audio
NO
YES - LOCK interrupt
generated
NO
YES - UNLOCK
interrupt generated
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
•
•
•
•
Wait a user defined
amount of time -
then increase
oversampling clock
to achieve lock.
Service UNLOCK interrupt
Disable UNLOCK interrupt
Enable LOCK interrupt
Disable capture and/or reset
(optional)
PNX15xx Series
Chapter 18: SPDIF Input
18-9