PNX1501E NXP Semiconductors, PNX1501E Datasheet - Page 524

• Manufacturer Part Number: PNX1501E
• Description: Digital Signal Processors & Controllers (DSP, DSC) MEDIA PROCESSOR PNX15XX/266MHZ
• Manufacturer: NXP Semiconductors

Specifications of PNX1501E

• Product: DSPs
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-795
• Minimum Operating Temperature: 0 C
• Lead Free Status / Rohs Status: Details
• Other names: PNX1501E,557

Philips Semiconductors
Volume 1 of 1
3. Operation
12NC 9397 750 14321
Product data sheet
Figure 2:
OSCLK
Audio In Clock System and I/O Interface
SCK
WS
SD
SD1
SD2
SD3
(e.g. 64xfs)
(e.g. 256xfs)
0
3.1.1 Clock System Operation
3.1 Clock Programming
Figure 2
is a square wave Direct Digital Synthesizer (DDS). The DDS can be programmed to
emit frequencies from approximately 1 Hz to 40 MHz with a resolution of better than
0.3 Hz. The DDS and its control registers reside in the Clocks module outside the
Audio in Unit.
The output of the DDS is always sent on the OSCLK output pin. This output is
intended to be used as the 256 f
converters.
Software may change the DDS frequency setting dynamically, so as to adjust the
input sampling rate to track an application dependent master reference. Using the
DDS function, a high quality, low-jitter OSCLK is generated.
SCK and WS can be configured as input or output, as determined by the
SER_MASTER control field. As an output, SCK is a divided form of the OSCLK
output frequency. The SCKDIV register value is used to divide down the OSCLK
frequency. See
the SCK pin signal is used as the bit clock for serial-parallel conversion. The value of
SCKDIV is determined by
Remark: SCKDIV is in the range 0-255.
f AISCK
Serial To Parallel
Converter
=
illustrates the clocking capabilities of the Audio Input unit. Driving the system
--------------------------------- -
SCKDIV
div N+1
f AIOSCLK
div N+1
SER_MASTER
Section 4. on page 16-15
Rev. 2 — 1 December 2004
+
1
8
7
32
32
SCKDIV
WSDIV
RIGHT1[31:0]
RIGHT0[31:0]
LEFT0[31:0]
LEFT1[31:0]
RIGHT2[31:0]
LEFT2[31:0]
LEFT3[31:0]
RIGHT3[31:0]
Equation
s
or 384 f
AI domain
12:
0
0
s
for more details. Whether input or output,
system clock source for oversampling A/D
27MHz x 64
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
DDS in Clocks Module
Square Wave DDS
PNX15xx Series
Chapter 16: Audio Input
(12)
16-5