PNX1501E NXP Semiconductors, PNX1501E Datasheet - Page 674

• Manufacturer Part Number: PNX1501E
• Description: Digital Signal Processors & Controllers (DSP, DSC) MEDIA PROCESSOR PNX15XX/266MHZ
• Manufacturer: NXP Semiconductors

Specifications of PNX1501E

• Product: DSPs
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-795
• Minimum Operating Temperature: 0 C
• Lead Free Status / Rohs Status: Details
• Other names: PNX1501E,557

Philips Semiconductors
Volume 1 of 1
Table 2: LAN100 Registers
12NC 9397 750 14321
Product data sheet
Bit
15
14:13
12
11
10:9
8
7
6
5
4
3
2
1
0
Offset 0x07 201C
2
1
0
31:3
Symbol
RESET_PESMII
-
PHY_MODE
RESET_PERMII
-
SPEED
RESET_PE100X
FORCE_QUIET
NO_CIPHER
DISABLE_LINK_FAIL
RESET_PE10T
-
ENABLE_JABBER_
PROTECTION
BIT_MODE
-
TEST_
BACKPRESSURE
TEST_PAUSE
SHORTCUT_PAUSE_
QUANTA
Test Register (TEST)
…Continued
Acces
s
R/W
-
R/W
R/W
-
R/W
R/W
R/W
R/W
R/W
R/W
-
R/W
R/W
-
R/W
R/W
R/W
Value
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Rev. 2 — 1 December 2004
Description
This bit resets the Serial MII logic.
Unused
This bit configures the Serial MII logic with the connecting SMII
device type. Set this bit when connecting to a SMII PHY. Clear this
bit when connecting to a SMII MAC. When MAC is selected, the
SMII will operate at 100 Mb/s, full duplex.
This bit resets the Reduced MII logic.
Unused
This bit configures the Reduced MII logic for the current operating
speed. When set, 100 Mb/s mode is selected. When cleared,
10 Mb/s mode is selected.
This bit resets the PE100X module which contains the 4B/5B
symbol encipher/decipher logic. This effects the PE100X module
only.
When set, transmit data is quieted, which allows the contents of the
cipher to be output. When cleared, normal operation is enabled.
Effects PE100X module only.
When set, the raw transmit 5B symbols are transmitted without
ciphering. When cleared, normal ciphering occurs. Effects PE100X
module only.
When set, the 330ms Link Fail timer is disabled allowing for shorter
simulations. Removes the 330 mS link-up time before reception of
streams is allowed. When cleared, normal operation occurs.
Effects PE100X module only.
This bit resets the PE10T module which converts MII nibble streams
to the serial bit stream of 10T transceivers. Effects PE10T module
only.
Unused
This bit enables the Jabber Protection logic within the PE10T in
ENDEC mode. Jabber is the condition where a transmitter is stuck
on for longer than 50ms to prevent other stations from transmitting.
Effects PE10T module only.
When set, the MAC is in 10BASE-T ENDEC mode, which changes
decodes (such as EXCESS_DEFER) to be based on the bit clock
rather than the nibble clock.
Unused
Setting this bit will cause the MAC to assert back pressure on the
link. Back pressure causes the preamble to be transmitted, raising
carrier sense. A transmit packet from the system will be sent during
back pressure.
This bit causes the MAC Control sublayer to inhibit transmissions,
just as if a PAUSE Receive Control frame with a non-zero pause
time parameter was received.
This bit reduces the effective PAUSE Quanta from 64 byte-times to
1 byte-time.
Chapter 23: LAN100 — Ethernet Media Access Controller
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
PNX15xx Series
23-12