PNX1501E NXP Semiconductors, PNX1501E Datasheet - Page 686

• Manufacturer Part Number: PNX1501E
• Description: Digital Signal Processors & Controllers (DSP, DSC) MEDIA PROCESSOR PNX15XX/266MHZ
• Manufacturer: NXP Semiconductors

Specifications of PNX1501E

• Product: DSPs
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-795
• Minimum Operating Temperature: 0 C
• Lead Free Status / Rohs Status: Details
• Other names: PNX1501E,557

Philips Semiconductors
Volume 1 of 1
Table 2: LAN100 Registers
12NC 9397 750 14321
Product data sheet
Bit
1
0
Offset 0x07 2FE8
The Interrupt Clear register is write-only. Writing a 1 to a bit of the register clears the corresponding bit in the Status register.
Writing a 0 to a bit of the register does not affect the corresponding interrupt status.
31:14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Offset 0x07 2FEC
The interrupt set register is write-only. Writing a 1 to a bit of the register sets the corresponding bit in the Status register.
Writing a 0 to a bit of the register does not affect the interrupt status.
31:14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Symbol
RxErrorIntEn
RxOverrunIntEn
-
WakeupIntSet
SoftIntSet
TxRtDoneIntSet
TxRtFinishedIntSet
TxRtErrorIntSet
TxRtUnderrunIntSet
TxDoneIntSet
TxFinishedIntSet
TxErrorIntSet
TxUnderrunIntSet
RxDoneIntSet
RxFinishedIntSet
RxErrorIntSet
RxOverrunIntSet
-
WakeupIntSet
SoftIntSet
TxRtDoneIntSet
TxRtFinishedIntSet
TxRtErrorIntSet
TxRtUnderrunIntSet
TxDoneIntSet
TxFinishedIntSet
TxErrorIntSet
TxUnderrunIntSet
RxDoneIntSet
RxFinishedIntSet
RxErrorIntSet
RxOverrunIntSet
Interrupt Clear Register (IntClear)
Interrupt Set Register (IntSet)
…Continued
Acces
s
R/W
R/W
-
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
-
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
Value
Rev. 2 — 1 December 2004
Description
Enable interrupts on receive errors.
Enable interrupts on receive buffer overrun or descriptor underrun
conditions.
Unused
Writing a 1 clears the corresponding status bit in IntStatus.
Writing a 1 clears the corresponding status bit in IntStatus.
Writing a 1 clears the corresponding status bit in IntStatus.
Writing a 1 clears the corresponding status bit in IntStatus.
Writing a 1 clears the corresponding status bit in IntStatus.
Writing a 1 clears the corresponding status bit in IntStatus.
Writing a 1 clears the corresponding status bit in IntStatus.
Writing a 1 clears the corresponding status bit in IntStatus.
Writing a 1 clears the corresponding status bit in IntStatus.
Writing a 1 clears the corresponding status bit in IntStatus.
Writing a 1 clears the corresponding status bit in IntStatus.
Writing a 1 clears the corresponding status bit in IntStatus.
Writing a 1 clears the corresponding status bit in IntStatus.
Writing a 1 clears the corresponding status bit in IntStatus.
Unused
Writing a 1 sets the corresponding status bit in IntStatus.
Writing a 1 sets the corresponding status bit in IntStatus.
Writing a 1 sets the corresponding status bit in IntStatus.
Writing a 1 sets the corresponding status bit in IntStatus.
Writing a 1 sets the corresponding status bit in IntStatus.
Writing a 1 sets the corresponding status bit in IntStatus.
Writing a 1 sets the corresponding status bit in IntStatus.
Writing a 1 sets the corresponding status bit in IntStatus.
Writing a 1 sets the corresponding status bit in IntStatus.
Writing a 1 sets the corresponding status bit in IntStatus.
Writing a 1 sets the corresponding status bit in IntStatus.
Writing a 1 sets the corresponding status bit in IntStatus.
Writing a 1 sets the corresponding status bit in IntStatus.
Writing a 1 sets the corresponding status bit in IntStatus.
Chapter 23: LAN100 — Ethernet Media Access Controller
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
PNX15xx Series
23-24