PNX1501E NXP Semiconductors, PNX1501E Datasheet - Page 433

• Manufacturer Part Number: PNX1501E
• Description: Digital Signal Processors & Controllers (DSP, DSC) MEDIA PROCESSOR PNX15XX/266MHZ
• Manufacturer: NXP Semiconductors

Specifications of PNX1501E

• Product: DSPs
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-795
• Minimum Operating Temperature: 0 C
• Lead Free Status / Rohs Status: Details
• Other names: PNX1501E,557

Philips Semiconductors
Volume 1 of 1
Table 6: Output Pixel Formats
12NC 9397 750 14321
Product data sheet
Format
planar YUV (4:4:4,
4:2:2) or RGB
semi planar YUV
(4:2:2)
packed 4/4/4 RGBa
packed 4/5/3 RGBa
packed 5/6/5 RGB
packed YUY2 4:2:2
packed UYVY 4:2:2
packed 888 RGB(a)
packed 4:4:4 VYU(a) (alpha)
2.5.6 Video Data Write to Memory
3
1
plane #1
plane #2
plane #3
plane #1
plane #2
(alpha)
3
0
Color Space Matrix Mode
In addition to normal and transposed polyphase filtering (scaling), the FIR filter
structure can instead be programed to perform color space-conversion. A dedicated
set of registers holds the coefficients for the color-space matrix. Horizontal scaling
and color space conversion are mutually exclusive.
The VIP can produce a variety of output formats. Video formats range from a single-
component up to three-component formats (like a 4:4:4 YUV). Up to three write
planes can be defined. On the input, the video format is restricted to YUV 4:2:2 as
defined in ITU-R-656 or 8/10 raw data. On the output, true color and compressed
formats are supported. For a complete list of supported video formats, refer to
Section 3. Register
The Pixel Packing Unit takes care of quantization and packing of the color
components into 64-bit units. A list of the most common video formats supported is
shown in
while bytes within one pixel unit are ordered according to the endian mode settings
(specified by the global endian mode register; endian mode bit in the output format
register can, however, invert that signal).
Table 6
mode. The selected endian mode will affect the position of the components within a
multi-byte pixel unit!
Remark: VIP does not explicitly support a 4:2:0 memory format. Such a format can
be obtained by discarding partial data written to memory.
2
9
2
8
2
7
shows the location of the first ’pixel unit’ within a 64-bit word in the little endian
Table
2
6
2
5
6. Packing of a pixel into 64-bit units is always done from right to left
2
4
Rev. 2 — 1 December 2004
2
3
R8 or Y8
V8
Descriptions.
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
alpha
alpha
R5
U8 or V8
Y8
G8 or U8
Y8
1
4
Chapter 12: Video Input Processor
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
1
3
1
2
1
1
R4
R4
PNX15xx Series
1
0 9 8 7 6 5 4 3 2 1 0
G6
Y8 or R8
U8 or G8
V8 or B8
Y8 or R8
U8/V8
G4
G5
Y8
U8 or V8
B8 or V8
U8
B5
B4
B3
12-13