PNX1501E NXP Semiconductors, PNX1501E Datasheet - Page 369

• Manufacturer Part Number: PNX1501E
• Description: Digital Signal Processors & Controllers (DSP, DSC) MEDIA PROCESSOR PNX15XX/266MHZ
• Manufacturer: NXP Semiconductors

Specifications of PNX1501E

• Product: DSPs
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-795
• Minimum Operating Temperature: 0 C
• Lead Free Status / Rohs Status: Details
• Other names: PNX1501E,557

Philips Semiconductors
Volume 1 of 1
3. Programming and Resource Assignment
12NC 9397 750 14321
Product data sheet
3.1 MMIO and Task Based Programming
In order for the QVCP to function properly its various block have to be configured.
Each functional unit contains a set of programming registers. A more detailed
description of the various registers can be found in the register description section of
this document.
The registers are divided in layer specific registers and global registers. Layer specific
registers are used to set up the layer related functions such as layer position, size,
pixel format and various conversion functions. The global register space
accommodates functions such as screen timing and output format related functions.
Another important part of the global register space are the resource assignment
registers which allow to assign the pool resources to specific layers.
There are two ways to access the QVCP registers:
The data structure to be used contains a header consisting of a pointer to the next
packet in memory. A null pointer indicates the last packet in a linked list. The header
also contains a field ID field which allows field synchronized insertion of VBI or re-
programming packets. Packet insertion can cause an interrupt if the appropriate
header flag is set. A detailed view of the packet format can be found in
Each data packet consists of an 8-byte descriptor followed by data (see
Table 5: Data Packet Descriptor
Bit
12:0
13
14
15
27:16
30:28
1. The first and primary way to get read/write access to the registers is via the
2. The second way to get write-only access to the registers is via data structures
MMIO bus, which maps the registers into the overall PNX15xx Series address
space.
fetched through the VBI DMA access port (used to fetch VBI data which get
inserted into the output data stream). Differentiation between VBI and
programming data is accomplished via a different header.
Description
Data byte count
Unused
1=wait for proper vertical field
0=send data on current field without considering the field ID (for a series of packets to
be inserted in the same field, this bit should only be set for the first packet and not for
subsequent ones. If this bit is set for all packets, they will be inserted with one field
delay each).
1=generate interrupt when this packet is transmitted
0=don’t generate packet interrupt
Screen line in which to insert the data packet
0=first line after rising edge of VSYNC
0xFFF=line compare disabled. The packet is inserted without consideration of the
line counter.
Field ID for this packet to be sent on
Rev. 2 — 1 December 2004
© Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved.
PNX15xx Series
Chapter 11: QVCP
Figure
Table
7.
5.)
11-23