PC87109VBE Nuvoton Technology Corporation of America, PC87109VBE Datasheet
PC87109VBE
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PC87109VBE Summary of contents
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... PC87109VBE Advanced UART and Infrared Controller General Description The PC87109 is a serial communication device with infrared capability. It supports 6 modes of operation and is backward compatible with the 16550 and 16450 (except for the MODEM control functions). The operational modes are: UART, Sharp-IR, IrDA 1.0 SIR, IrDA 1.1 MIR and FIR, and Consumer Electronics IR (also referred Remote or Consumer Remote Control) ...
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Table Of Contents 1. Pin Description 1.1 Connection Diagram 1.2 Pin Description 2. Functional Description 2.1 Device Overview 2.2 UART Mode 2.3 Sharp-IR Mode 2.4 IrDA 1.0 SIR Mode 2.5 IrDA 1.1 MIR and FIR Modes 2.5.1 High Speed Infrared ...
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SH_LCR - Link Control Register Shadow, Read Only 3.4.3 SH_FCR - FIFO Control Register Shadow, Read Only 3.4.4 LCR/BSR - Link Control/Bank Select Registers 3.5 Bank 4 3.5.1 TMR - Timer Register 3.5.2 IRCR1- Infrared Control Register 1 3.5.3 ...
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List Of Figures Figure 1-1. 32-Pin TQFP Package Figure 1-2. Basic Configuration Figure 2-1. Serial Data Stream Fromat Figure 3-1. Register Bank Architecture Figure 3-2. Interrupt Enable Register Figure 3-3. Event Identification Register, Non-Extended Mode Figure 3-4. Event Identification Register, ...
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5 www.national.com ...
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List Of Tables Table 3-1. Register Banks Summary Table 3-2. Bank 0 Register Set Table 3-3. Non-Extended Mode Interrupt Priorities Table 3-4. Bank Selection Encoding Table 3-5. UIR Module Operational Modes Table 3-6. Bank 1 Register Set Table 3-7. Bank ...
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... Pin Descriptions 1.1 Connection Diagram IRQ DRQ PC87109VBE 8 Top View Figure 1-1. 32-Pin TQFP Package Order number PC87109VBE See NS package VBE32A 7 16 IRRX1 IRTX ID0/IRSL0/IRRX2 ID1/IRSL1 SOUT SIN 9 www.national.com ...
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Pin Descriptions Symbol Pin(s) SUPPLIES BUS INTERFACE SIGNALS A0-A3 7 D0-D7 21-27 DACK DRQ 32 IRQ UART INTERFACE ...
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A0-A3 D0 PC87109 CS TC DRQ ID0/IRSL0/IRRX2 DACK IRQ Figure 1-2. Basic Configuration 9 48MHz CLKIN Clock SIN EIA Interface SOUT IRRX1 IRTX XCVR IR Interface www.national.com ...
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Functional Description 2.1 Device Overview The PC87109 is a serial communications element that implements the most common infrared communications protocols. In addition to the infrared modes, the device provides a UART mode of operation that is backward compatible to ...
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IrDA 1.0 SIR Mode This is the first operational mode that has been defined by the IrDA committee and, similarly to Sharp-IR, it also supports bi-directional data communication with a remote device using infrared radiation as the transmission medium. ...
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TX_FIFO). 3. Reset TX_FIFO. Note: the setting of the DMA_EN bit in the extended-mode MCR register only controls PIO ...
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Logic 1 in the bit string will keep the LED off infrared signal is transmitted. A logic 0 will generate a sequence of modulating ...
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More than 64 s have elapsed since the last byte was read from the RX_FIFO by the CPU or DMA controller. ST_FIFO Time-out Conditions least one entry is in the ST_FIFO, and 2. More than 1 ms ...
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Optical Transceiver Interface The PC87109 implements a very flexible interface for the external infrared transceiver. Several signals are provided for this purpose. A transceiver module with one or two receive signals can be directly interfaced without any additional logic. ...
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Architectural Description Eight register banks are provided to control the operation of the UIR module. These banks are mapped into the same address range, and only the selected bank is directly accessible by the software. The address range spans ...
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Bank 0 Address Offset 3.1.1 TXD/RXD - Transmit/Receive Data Ports These ports share the same address. TXD is accessed during CPU write cycles. It provides the write data path to the ...
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B2 UART, Sharp-IR, SIR Modes LS_IE - Link Status Interrupt Enable. MIR, FIR, CEIR Modes LS_IE/TXHLT_IE - Link Status/Transmitter Halted Interrupt Enable. B3 Reserved Read/Write DMA_IE - DMA Interrupt Enable. B5 TXEMP_IE - Transmitter Empty Interrupt Enable. ...
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EIR bits Priority Interrupt 3210 Level Type 0001 N/A None 0110 Highest Line Status 0100 Second Receiver High-Data- Level Event 1100 Second RX_FIFO Time-out 0010 Third Transmitter Low-Data-Level Event Table 3-3. Non-Extended Mode Interrupt Priorities Extended Mode The EIR register ...
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Note: A high speed CPU can service the interrupt generated by the last frame byte reaching the RX_FIFO bottom before that byte is transferred to memory by the DMA controller. This can happen when the CPU interrupts latency is shorter ...
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B7-6 RXFTH [1-0] - RX_FIFO Interrupt Threshold. These bits select the RX_FIFO interrupt threshold level. An interrupt is generated when the RX_FIFO level is equal to or above the threshold. Bits 7 3.1.4 LCR/BSR - Link ...
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B6 SBRK - Set Break. When set to 1, the following occurs: If UART mode is selected, the SOUT pin is forced to logic 0 state. If SIR mode is selected, pulses are issued continuously on the IRTX pin. If ...
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B4 LOOP – Loop-back Enable. When set to 1, loop-back mode is selected. This bit accesses the same internal register as bit 4 of the EXCR1 register. Refer to the section describing the EXCR1 register for more information on the ...
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Note: This register is intended for read operations only. Writing to this register is not recommended as it may cause indeterminate results. Bits B7 B6 Function. ER_INF/ TXEMP FR_END Reset State RXDA - Receiver Data Available. Set ...
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MIR Mode PHY_ERR - Physical Layer Error. Set to 1 when an abort condition is detected during the reception of a frame, and the last byte of the frame has reached the bottom of the RX_FIFO. Cleared upon read. FIR ...
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ASCR - Auxiliary Status and Control Register. This register is accessed when the extended mode of operation is selected. All the ASCR bits are cleared when hardware reset occurs. Bits 2 and 6 are cleared when the transmitter is soft ...
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B6 MIR, FIR, CEIR Modes TXUR - Transmitter Under-run. This bit is set to 1 when a transmitter under-run occurs always cleared when a mode other than MIR, FIR or CEIR is selected. This bit must be cleared, ...
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BGD - Baud Generator Divisor Port This port provides the data path to the baud generator divisor register that holds the reload value for the baud generator counter. 16 Divisor values from can be ...
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B0 EXT_SL - Extended Mode Select. 0 => Legacy mode is selected 1 => Extended mode is selected. When the extended mode is selected, the device architecture changes slightly and a variety of additional features are made available. The interrupt ...
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RECEIVER RX_DMA CHANNEL DMA LOGIC TX_DMA TRANSMITTER CHANNEL DMA LOGIC 3.3.3 LCR/BSR - Link Control/Bank Select Registers These registers are the same as in bank 0. 3.3.4 EXCR2 - Extended Control Register 2 This register is used to configure the ...
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B7 LOCK - Lock Bit. When set to 1, accesses to the baud generator divisor register through LBGDL and LBGDH as well as fallback are disabled from non-extended mode. In this case two scratchpad registers overlaid with LBGDL and LBGDH ...
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SH_FCR - FIFO Control Register Shadow, Read Only This register returns the value written into the FCR register in bank 0. 3.4.4 LCR/BSR - Link Control/Bank Select Registers These registers are the same as in bank 0. 3.5 Bank ...
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B3-2 IR_SL [1-0] - SIR or Sharp-IR Select, Non-Extended Mode Only. These bits are used to select the appropriate infrared mode when the device is in non-extended mode. They are ignored when extended mode is selected. Bits 3-2 Selected Mode ...
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LCR/BSR - Link Control/Bank Select Registers These registers are the same as in bank 0. 3.6.2 IRCR2 - Infrared Control Register 2 Upon reset, the content of this register is 02h. Bits B7 B6 Function res SFTSL Reset State ...
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FRM_ST - Frame Status Byte at ST_FIFO Bottom, Read Only This register returns the status byte at the bottom of the ST_FIFO. If the LOST_FR bit is 0, bits indicate if any error condition occurred during ...
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Bank 6 Address Offset 5-7 3.7.1 IRCR3 - Infrared Control Register 3 Used to select the operating mode of the infrared interface. Upon reset, the content of this register is 20h. Bits B7 B6 ...
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B3-0 MPW [3-0] - MIR Signal Pulse Width Encoding Pulse Width, MDRS = 0 00XX Reserved 0100 0101 104.1 ns 0110 125.0 ns 0111 145.8 ns 1000 166.6 ns 1001 187.5 ns 1010 208.3 ns 1011 229.1 ns 1100 250.0 ...
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Encoding Preamble Length 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 B7-4 MBF [3-0] - MIR Beginning Flags. Selects the number of beginning flags for MIR frames. Encoding Beginning Flags 0000 0001 0010 0011 0100 0101 0110 ...
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B4-0 DFR [4-0] - Demodulator Frequency. These bits determine the subcarrier' center frequency for the CEIR mode. B7-5 DBW [2-0] - Demodulator Bandwidth. These bits determine the demodulator bandwidth within which the subcarrier signal frequency has to fall in order ...
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B4-0 MCFR [4-0] - Modulation Sub-carrier Frequency. Selects the frequency for the CEIR modulation sub-carrier. Encoding Low Frequency, TXHSC = 0 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 ...
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B1-0 RC_MMD [1-0] - Transmitter Modulation Mode. Determines how infrared pulses are generated from the transmitted bit string. 00 => C_PLS Modulation Mode. Pulses are generated continuously for the entire logic 0 bit time 01 => 8_PLS Modulation Mode. 8 ...
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B0 IRIC0 - Transceiver Identification/Control. The function of this bit depends on whether the ID0/IRSL0/IRRX2 pin is programmed as input output. ID0/IRSL0/IRRX2 Pin Programmed as Input (IRSL0_DS = 0). Upon read, this bit returns the logic level ...
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B6 IRRX_MD - IRRX Mode Select. Determines whether a single input or two separate inputs are used for Low-Speed and High-Speed IrDA modes. 0 => One input is used for both SIR and MIR/FIR. 1 => Separate inputs are used ...
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Device Configuration 4.1 Overview On power-up or after a hardware reset, the PC87109 will have all of its modules and functions disabled. The ID/IRSL [1-0] pins are in input mode. The IRTX and the UART output pin are set ...
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B4 IRQBC -- IRQ Output Buffer Configuration. This bit determines whether the IRQ output buffer is configured as Open Drain or Totem Pole. Value Output Buffer Type 0 Open Drain 1 Totem Pole B5 DRQINV – DRQ Polarity Invert. When ...
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B0 DEV_EN -- Device Enable. When set to 1, the device is enabled. When this bit is 0, the device is disabled and the following occurs: 1. All internal modules are powered down. 2. Accesses to the UIR module registers ...
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Device Specifications 5.1 Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. -0. 7.0V Supply Voltage ( Input Voltage (V ) -0.5 to ...
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Symbol Parameter Output TRI-STATE I OZ Leakage Current UART INTERFACE SIGNALS Output High Voltage V OH Output Low Voltage V OL Input Load Current I IL INFRARED INTERFACE SIGNALS Output High Voltage V OH Output Low Voltage V OL Input ...
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Symbol t Data Bus Floating From Read Inactive HZ t Address Hold from Read Inactive RA t Read Cycle Recovery RRV t Read Strobe Width RD t Read Data Hold RDH t Data Valid From Read Active RDV Address Hold ...
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Symbol t MIR Leading Edge Jitter. MJT Percent of Nominal Bit Duration. t MIR Pulse Width MPW F FIR Data Rate Tolerance. DRT Percent of Nominal Data Rate. FIR Leading Edge Jitter. t FJT Percent of Nominal Chip Duration. t ...
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Timing Diagrams CLK CS A0- IRQ D0- Figure 5-2. Clock Timing Valid RRV CSS t CSH RDV RDH ...
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CS A0-A3 Valid CSS RD IRQ D0-D7 Figure 5-4. CPU Write Timing DRQ t DACK RD Figure 5-5. DMA Access Timing Valid WRV CSH t WI ...
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UART t CMW Sharp-IR Consumer-IR - Figure 5-6. UART, Sharp-IR and CEIR Timing t SPW SIR t MPW MIR t FPW FIR Note: The signals shown here represent the infrared signals at the IRTX output. The infrared signals at the ...
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Figure 5-9. Reset Timing www.national.com ...
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... Physical Dimensions 32-Pin Thin Quad Flat Pack inches(millimeters) Figure 6-1. Thin Plastic Quad Flat Pack Order Number PC87109VBE NS Package Number VBE32A 55 www.national.com ...
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LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR COPORATION. As used herein: 1. Life support devices or systems ...