PC87109VBE Nuvoton Technology Corporation of America, PC87109VBE Datasheet - Page 23

• Manufacturer Part Number: PC87109VBE
• Description: IC CONTROLLER ADV UART 32-LQFP
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of PC87109VBE

• Features: Transmit Deferral
• Number Of Channels: 2, DUART
• Fifo's: 16 Byte
• Voltage - Supply: 5V
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *PC87109VBE

Extended Mode
The format of the extended mode MCR is shown in figure 3-8.
Note: Bits 2 to 7 should always be initialized when the operational mode is changed from non-extended to extended
3.1.6 LSR - Link Status Register
This register provides status information to the CPU concerning the data transfer.
Bits 1 through 4, and 5 (when in MIR or FIR mode) indicate link status events.
These bits are sticky, and accumulate any conditions occurred since the last time the register was read.
These bits are cleared when any of the following events occurs:
1. Hardware reset.
2. The receiver is soft reset.
3. The LSR register is read.
B4
B7-5
Bits
Function
Reset State
B0-1
B2
B3
B4
B7-5
LOOP – Loop-back Enable.
When set to 1, loop-back mode is selected.
This bit accesses the same internal register as bit 4 of the EXCR1 register.
Refer to the section describing the EXCR1 register for more information on the loop-back mode.
Reserved.
Forced to 0.
Reserved.
Read/Write as 0.
DMA_EN - DMA Mode Enable.
When set to 1, DMA mode of operation is enabled.
When data transfers are performed by a DMA controller transmit and/or receive data interrupts should be disabled
to avoid spurious interrupts.
Note that DMA cycles always access the data holding registers or FIFOs, regardless of the selected bank.
TX_DFR - Transmit Deferral.
When set to 1, transmit deferral is enabled.
Effective only when the TX_FIFO is enabled.
IR_PLS - Send Interaction Pulse.
This bit is effective only in MIR and FIR Modes.
It is set to 1 by writing 1 into it.
Writing 0 into it has no effect.
When set to 1, a 2 s infrared interaction pulse is transmitted at the end of the frame and the bit is automatically
cleared by the hardware.
This bit is also cleared when the transmitter is soft reset.
MDSL [2-0] - Mode Select.
These bits are used to select the operational mode as shown in Table 3-5.
When the mode is changed, the transmitter and receiver are soft reset.
MDSL2
B7
0
MDSL1
B6
0
Figure 3-8. Mode Control Register, Extended Mode
Table 3-5. UIR Module Operational Modes
MDSL0
7 6 5
Bits
000
001
010
011
100
101
110
111
B5
0
UART
Reserved
Sharp-IR
SIR
MIR
FIR
CEIR
Reserved
Operational Mode
IR_PLS
23
B4
0
TX_DFR
B3
0
DMA_EN
B2
0
.
B1
res
0
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res
B0
0