PC87109VBE Nuvoton Technology Corporation of America, PC87109VBE Datasheet - Page 8

• Manufacturer Part Number: PC87109VBE
• Description: IC CONTROLLER ADV UART 32-LQFP
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of PC87109VBE

• Features: Transmit Deferral
• Number Of Channels: 2, DUART
• Fifo's: 16 Byte
• Voltage - Supply: 5V
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *PC87109VBE

1.2 Pin Descriptions
SUPPLIES
V
V
BUS INTERFACE SIGNALS
A0-A3
CS
D0-D7
DACK
DRQ
IRQ
MR
RD
TC
WR
UART INTERFACE SIGNALS
SIN
SOUT
INFRARED INTERFACE SIGNALS
IRRX1
ID0/IRSL0/IRRX2
ID1/IRSL1
IRTX
MISCELLANEOUS SIGNALS
CLKIN
RESERVED
DD
SS
Symbol
13, 28
12, 29
7-4
3
21-27, 30
1
32
31
8
19
2
20
9
10
16
14
11
15
17
18
Pin(s)
Type
NC
I/O
I/O
I/O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
5V or 3.3V Power Supply
Ground.
Address. Input signals used to determine which internal register is accessed
(Section 4.2). A0-A3 are ignored during a DMA access.
Chip Select. Active low input used in conjunction with A0-A3 to select the internal
registers.
Data Bus. 8-bit bi-directional data lines used to transfer data between the PC87109
and the CPU or DMA controller. D0 is the LSB and D7 is the MSB
DMA Acknowledge. Used to acknowledge a DMA request and enable the RD or
WR signals during a DMA access cycle. The polarity of this signal is programmable.
DMA Request. Used to signal the DMA controller that a data transfer from the
PC87109 is required. The polarity of this signal is programmable.
Interrupt Request. This output is used to signal an interrupt condition to the CPU
(Section 4.2.2). The IRQ signal can be configured to be either open-drain or totem
pole. Its polarity is also programmable.
Master Reset. A low level on this input resets the PC87109. This signal
asynchronously terminates any activity and places the device in the Disable state.
Read. Active low input asserted by the CPU or DMA controller to read data or status
information from the PC87109.
Terminal Count. This signal is asserted by the DMA controller to indicate the end of
a DMA transfer. The signal is only effective during a DMA access cycle. Its polarity is
programmable.
Write. Active low input asserted by the CPU or DMA controller to write data or
control information to the PC87109.
Serial Data In. This input receives serial data from the communications link.
Serial Data Out. This output sends serial data to the communications link. This
signal is set to a Marking state (logic 1) after a Master Reset operation or when the
device is in one of the Infrared communications modes.
Infrared Receive. Primary input to receive serial data from the infrared transceiver
module. If the infrared transceiver provides two receive data outputs, the low-speed
output should be connected to this pin.
Transceiver Identification, Control or Secondary Infrared Receive.
Transceiver Identification or Control. Used to read identification data to support
infrared adapters, as well as to select the transceiver operational mode.
Infrared Transmit. This output sends serial data to the transceiver module(s).
Clock. 48 MHz clock input.
Reserved. No connection should be made on this pin.
Multi function pin implementing the following functions:
- ID0, to read identification data to support infrared adapters.
- IRSL0, to select the transceiver operational mode.
- IRRX2, used either as a high-speed receiver input (for MIR and FIR) to support
to support two transceiver modules.
transceiver modules with two receive data outputs, or as an auxiliary input
8
Description
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