PC87109VBE Nuvoton Technology Corporation of America, PC87109VBE Datasheet - Page 27

• Manufacturer Part Number: PC87109VBE
• Description: IC CONTROLLER ADV UART 32-LQFP
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of PC87109VBE

• Features: Transmit Deferral
• Number Of Channels: 2, DUART
• Fifo's: 16 Byte
• Voltage - Supply: 5V
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *PC87109VBE

3.2 Bank 1
3.2.1 LBGD - Legacy Baud Generator Divisor Port
This port provides an alternate data path to the baud generator divisor register. It is implemented for compatibility with the
16550 and to support existing legacy software packages. New software should use the BGD port in bank 2 to access the baud
generator devisor register. Like the BGD port, LBGD is 16 bits wide and is split into two 8-bit parts, LBGDL and LBGDH,
occupying consecutive address locations. A CPU read or write access of the divisor register, through either LBGDL or LBGDH,
will affect the device operational mode as follows.
If the device is in extended mode, the device is switched back to 16550-compatibility mode.
In addition to the EXT_SL bit, the following bits are also cleared.
1. Bits 2 to 7 of extended-mode MCR.
2. Bit 5 and 7 of EXCR1.
3. Bits 0 to 5 of EXCR2.
4. Bits 2 and 3 of IRCR1.
1. Bits 5 and 7 of EXCR1.
2. Bits 0 to 5 of EXCR2.
If the device is in non-extended mode and the LOCK bit is 1, the content of the divisor register will not be affected and no other
action is taken.
3.2.2 LCR/BSR - Link Control/Bank Select Registers
These registers are the same as in bank 0.
3.3 Bank 2
If the device is in non-extended mode and the LOCK bit is 0, the following bits will be cleared.
B6
B7
MIR, FIR, CEIR Modes
MIR, FIR, SIR Modes
TXUR - Transmitter Under-run.
This bit is set to 1 when a transmitter under-run occurs.
It is always cleared when a mode other than MIR, FIR or CEIR is selected.
This bit must be cleared, by writing 1 into it, to re-enable transmission.
CTE - Clear Timer Event.
Writing 1 into this bit position clears the TMR_EV bit in the EIR register. Writing 0 into it has no effect.
Address
Offset
4-7
Address
0
1
2
3
Offset
0
1
2
3
4
5
6
7
Reserved
LCR/BSR
Reserved
LBGDL
LBGDH
Register
Name
BGDL
BGDH
EXCR1
LCR/BSR
EXCR2
Reserved
TXFLV
RXFLV
Register
Name
Table 3-6. Bank 1 Register Set
Table 3-7. Bank 2 Register Set
Legacy Baud Generator Divisor Port Low Byte
Legacy Baud Generator Divisor Port High-Byte
Link Control/Bank Select Registers
Baud Generator Divisor Port Low-Byte
Baud Generator Divisor Port High-Byte
Extended Control Register 1
Link Control / Bank Select Registers
Extended Control Register 2
TX_FIFO Level
RX_FIFO Level
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Description
Description
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