PC87109VBE Nuvoton Technology Corporation of America, PC87109VBE Datasheet - Page 32

• Manufacturer Part Number: PC87109VBE
• Description: IC CONTROLLER ADV UART 32-LQFP
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of PC87109VBE

• Features: Transmit Deferral
• Number Of Channels: 2, DUART
• Fifo's: 16 Byte
• Voltage - Supply: 5V
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *PC87109VBE

3.4.3 SH_FCR - FIFO Control Register Shadow, Read Only
This register returns the value written into the FCR register in bank 0.
3.4.4 LCR/BSR - Link Control/Bank Select Registers
These registers are the same as in bank 0.
3.5 Bank 4
3.5.1 TMR - Timer Register
This register is used to program the reload value for the internal down counter as well as to read the current counter value. TMR
is 12 bits wide and is split into two independently accessible parts occupying consecutive address locations. TMRL is located at
the lower address and accesses the least significant 8 bits, whereas TMRH is located at the higher address and accesses the
most significant 4 bits. Values from 1 to 2
of TMRH are reserved and must be written with 0's. The timer resolution is 125 s, providing a maximum time-out interval of
approximately 0.5 seconds. To properly program the timer, the CPU must always write the lower value into TMRL first and then
the upper value into TMRH. Writing into TMRH causes the counter to be loaded. A read of TMR returns the current counter
value if the CTEST bit is 0, or the programmed reload value if CTEST is 1. In order for a read access to return an accurate
value, the CPU should always read TMRL first, and then TMRH. This is because a read of TMRH returns the content of an
internal latch that is loaded with the 4 most significant bits of the current counter value when TMRL is read. After reset, the
content of this register is indeterminate.
3.5.2 IRCR1- Infrared Control Register 1
Used to control the timer and counters as well as enable the Sharp-IR or SIR infrared mode in the non-extended mode of
operation. Upon reset, all bits are set to 0.
B0
B1
Bits
Function
Reset State
TMR_EN - Timer Enable, Extended Mode Only.
When this bit is 1, the timer is enabled.
When it is 0, the timer is frozen.
CTEST - Counters Test.
When this bit is set to 1, the TMR register reload value, as well as the TFRL and RFRML register contents are
returned during CPU reads.
res
B7
0
Address
Offset
res
B6
0
0
1
2
3
4
5
6
7
12
Figure 3-16. Infrared Control Register 1
- 1 can be used. The zero value is reserved and must not be used. The upper 4 bits
TMRL
TMRH
IRCR1
LCR/BSR
TFRLL/
TFRCCL
TFRLH/
TFRCCH
RFRMLL/
RFRCCL
RFRMLH/
RFRCCH
Register
Table 3-10. Bank 4 Register Set
Name
res
B5
0
Timer Register Low-Byte
Timer Register High-Byte
Infrared Control Register 1
Link control/Bank Select registers
Transmitter Frame Length/
Current Count Low Byte
Transmitter Frame Length/
Current Count High Byte
Receive Frame Maximum Length/
Current Count (Low Byte)
Receive Frame Maximum Length/
Current Count High Byte
32
res
B4
0
Description
IR_SL1
B3
0
IR_SL0
B2
0
CTEST
B1
0
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TMR_EN
B0
0