PC87109VBE Nuvoton Technology Corporation of America, PC87109VBE Datasheet - Page 29

• Manufacturer Part Number: PC87109VBE
• Description: IC CONTROLLER ADV UART 32-LQFP
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of PC87109VBE

• Features: Transmit Deferral
• Number Of Channels: 2, DUART
• Fifo's: 16 Byte
• Voltage - Supply: 5V
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *PC87109VBE

B0
B1
B2
B3
B4
B5
B6
B7
EXT_SL - Extended Mode Select.
0 => Legacy mode is selected
1 => Extended mode is selected.
When the extended mode is selected, the device architecture changes slightly and a variety of additional features
are made available. The interrupt sources are no longer prioritized, and an auxiliary status and control register
replaces the scratch pad register. The additional features include transmitter FIFO thresholding, DMA capability,
and interrupts on transmitter empty and DMA event.
DMANF - DMA Fairness Control.
This bit controls the maximum duration of DMA burst transfers.
0 => DMA requests are forced inactive after approximately 10.5 s of continuous transmitter and/or receiver DMA
1 => A TX_DMA request is deactivated when the TX_FIFO is full.
DMATH - DMA Threshold Levels Select.
This bit selects the TX_FIFO and RX_FIFO threshold levels used by the DMA request logic to support demand
transfer mode.
A TX_DMA request is generated when the TX_FIFO level is below the threshold.
An RX_DMA request is generated when the RX_FIFO level reaches the threshold or when an RX_FIFO time-out
occurs.
DMASWP - DMA Swap.
LOOP – Loop-back Enable.
When set to 1, loop-back mode is selected.
This bit accesses the same internal register as bit 4 in the MCR register, when the device is in non-extended mode.
During loop-back the following occur:
1. The DMA control signals are fully operational.
2. UART input (SIN) and infrared receiver (IRRX1, 2) input pins are disconnected. The internal receiver inputs are
3. The UART transmitter serial output (SOUT) is forced high and the infrared transmitter serial output (IRTX) is
ETDLBK - Enable Transmitter Output During Loop-back.
When set to 1, the transmitter serial output is enabled and functions normally when loop-back is selected.
Reserved.
Write 1.
BTEST - Baud Generator Test.
When set to 1, the output of the baud generator is routed to the ID1/IRSL1 pin.
This bit selects the routing of the DMA control signals between the internal DMA logic and the configuration
module. When this bit is 0, the external DMA handshake signals are routed to the internal receiver DMA channel.
When it is 1, they are routed to the internal DMA transmitter channel. A block diagram illustrating the control
signals routing is given in figure 3-13.
Loop-back mode behaves similarly in both non-extended and extended modes.
connected to the corresponding internal transmitter outputs.
forced low, unless the ETDLBK bit is set to 1, In which case they will function normally.
operation.
An RX_DMA request is deactivated when the RX_FIFO is empty.
Bit Value
0
1
RX_FIFO DMA Thresh.
10
4
TX_FIFO DMA Thresh.
29
(16-Levels)
13
7
TX_FIFO DMA Thresh.
(32- Levels)
29
23
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