PC87109VBE Nuvoton Technology Corporation of America, PC87109VBE Datasheet - Page 21

• Manufacturer Part Number: PC87109VBE
• Description: IC CONTROLLER ADV UART 32-LQFP
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of PC87109VBE

• Features: Transmit Deferral
• Number Of Channels: 2, DUART
• Fifo's: 16 Byte
• Voltage - Supply: 5V
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *PC87109VBE

3.1.4 LCR/BSR - Link Control/Bank Select Register
These registers share the same address.
The Link Control Register (LCR) is used to select the communications format for data transfers in UART, Sharp-IR and SIR
modes.
The Bank select register (BSR) is used to select the register bank to be accessed next.
When the CPU performs a read cycle from this address location, the BSR content is returned. The content of LCR is returned
when the CPU reads the SH_LCR register in bank 3.
During CPU write cycles, the setting of bit 7 (BKSE, bank select enable) determines the register to be accessed.
If bit 7 is 0, both LCR and BSR are written into. If bit 7 is 1, only BSR is written into, and LCR is not affected. This prevents the
communications format from being spuriously affected when a bank other than bank 0 is accessed. Upon reset, all bits are set to
0.
LCR - Link Control Register
The Format of LCR is shown in figure 3-6.
Bits 0 to 6 are only effective in UART, Sharp-IR and SIR modes.
They are ignored in MIR, FIR and CEIR modes.
Bits
Function
Reset State
B1-0
B2
B3
B4
B5
B7-6
RXFTH [1-0] - RX_FIFO Interrupt Threshold.
These bits select the RX_FIFO interrupt threshold level.
An interrupt is generated when the RX_FIFO level is equal to or above the threshold.
WLS [1-0] - Character Length.
These bits specify the length of each transmitted or received serial character.
STB - Stop Bits.
Number of stop bits in each transmitted serial character. If this bit is 0, 1 stop bit is generated in the transmitted
data. If it is 1 and a 5-bit character length is selected via bits 0 and 1, 1.5 stop bits are generated. If it is 1 and a 6,
7 or 8-bit character length is selected, 2 stop bits are generated. The receiver checks 1 stop bit only, regardless of
the number of stop bits selected.
PEN - Parity Enable.
When set to 1, parity bits are generated and checked by the transmitter and receiver channels respectively.
EPS - Even Parity.
Used in conjunction with the STKP bit to determine the parity bit. See encoding below.
STKP - Stick Parity.
The encoding of this and the previous two bits, for control of the parity bit, are as follows:
Bits 10
BKSE
00
01
10
11
B7
0
PEN
0
1
1
1
1
Character Length
Bits 7-6
00
01
10
11
SBRK
B6
0
5 Bits
6 Bits
7 Bits
8 Bits
EPS
x
0
1
0
1
Figure 3-6. Link Control Register
STKP
B5
0
RX_FIFO Thresh.
(16 Levels)
STKP
x
0
0
1
1
14
1
4
8
EPS
B4
21
0
Selected Parity
none
odd
even
logic 1
logic 0
PEN
B3
0
RX_FIFO Thresh.
(32 Levels)
16
26
STB
1
8
B2
0
WLS1
B1
0
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WLS0
B0
0