PC87109VBE Nuvoton Technology Corporation of America, PC87109VBE Datasheet - Page 26

• Manufacturer Part Number: PC87109VBE
• Description: IC CONTROLLER ADV UART 32-LQFP
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of PC87109VBE

• Features: Transmit Deferral
• Number Of Channels: 2, DUART
• Fifo's: 16 Byte
• Voltage - Supply: 5V
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *PC87109VBE

ASCR - Auxiliary Status and Control Register.
This register is accessed when the extended mode of operation is selected.
All the ASCR bits are cleared when hardware reset occurs.
Bits 2 and 6 are cleared when the transmitter is soft reset.
Bits 0, 1, 4 and 5 are cleared when the receiver is soft reset.
The format of ASCR is shown in figure 3-11.
Bits
Function
Reset State
B0
B1
B2
B3
B4
B5
MIR, FIR Modes
MIR, FIR Modes
CEIR Mode
MIR, FIR Modes
MIR, FIR Modes
CEIR Mode
MIR, FIR Modes
CEIR Mode
RXF_TOUT - RX_FIFO Time-out.
This bit is read-only, and is set to 1 when an RX_FIFO Time-out occurs.
In MIR or FIR modes this bit can be used in conjunction with bit 1 to determine whether a number of bytes as
determined by the RX_FIFO threshold, can be read without checking the RXDA bit in the LSR register for each
byte. Cleared when a character is read from the RX_FIFO.
EOF_INF - EOF Bytes in RX_FIFO.
This bit is read-only, and is set to 1 when one or more EOF bytes are in the RX_FIFO.
Cleared when no EOF byte is in the RX_FIFO.
S_EOT - Set End of Transmission.
When a 1 is written into this bit position before writing the last character into the TX_FIFO, frame transmission is
completed and a CRC + EOF is sent. This bit can be used as an alternative to the Transmitter Frame Length
register. If this method is to be used, the FEND_MD bit in the IRCR2 register should be set to 1, or the Transmitter
Frame Length register should be set to maximum count.
This bit is automatically cleared by the hardware when a character is written into the TX_FIFO.
S_EOT - Set End of Transmission.
When a 1 is written into this bit position before writing the last character into the TX_FIFO, data transmission is
gracefully completed. If the CPU simply stops writing data into the TX_FIFO at the end of the data stream, a
transmitter under-run is generated and the transmitter stops. In this case, this is not an error, however the
software needs to clear the under-run before the next transmission can occur.
TXHFE - Transmitter Halted on Frame End.
This bit is used only when the transmitter frame-end stop mode is selected (TX_MS bit in IRCR2 set to 1).
It is set to 1 by the hardware when transmission of a frame is complete and the TFRCC counter reaching 0
generated the end-of –frame condition.
This bit must be cleared, by writing 1 into it, to re-enable transmission.
LOST_FR - Lost Frame Flag.
This bit is read-only, and reflects the setting of the lost-frame indicator flag at the bottom of the ST_FIFO.
RXWDG - Receiver WATCHDOG.
Set to 1 each time an infrared pulse or the receiver detects pulse-train.
Can be used by the software to detect a receiver idle condition.
Cleared upon read.
RXBSY - Receiver Busy.
This bit is read-only, and returns a 1 when reception of a frame is in progress.
RXACT - Receiver Active.
Set to 1 when an infrared pulse or pulse-train is received. If a 1 is written into this bit position, the bit is cleared
and the receiver is deactivated. When this bit is set, the receiver samples the infrared input continuously at the
programmed baud rate and transfers the data to the RX_FIFO.
This bit is automatically cleared by the hardware when a character is written into the TX_FIFO.
CTE
B7
0
TXUR
B6
0
Figure 3-10. Auxiliary Status and Control Register
RXBSY/
RXACT
B5
0
LOST_FR/
RXWDG
B4
26
0
TXHFE
B3
0
S_EOT
B2
0
EOF_INF
B1
0
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RXF_TOUT
B0
0