PC87109VBE Nuvoton Technology Corporation of America, PC87109VBE Datasheet - Page 20

• Manufacturer Part Number: PC87109VBE
• Description: IC CONTROLLER ADV UART 32-LQFP
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of PC87109VBE

• Features: Transmit Deferral
• Number Of Channels: 2, DUART
• Fifo's: 16 Byte
• Voltage - Supply: 5V
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *PC87109VBE

Note: A high speed CPU can service the interrupt generated by the last frame byte reaching the RX_FIFO bottom before that byte is transferred to
memory by the DMA controller. This can happen when the CPU interrupts latency is shorter than the RX_FIFO Time-out (Refer to the ‘FIFO Time-
outs’ section). A DMA request is generated only when the RX_FIFO level reaches the DMA threshold or when a FIFO Time-out occurs, in order to
minimize the performance degradation due to DMA signal handshake sequences. If the DMA controller must be set up before receiving each frame,
the software in the interrupt routine should make sure that the last byte of the frame just received has been transferred to memory before re-
initializing the DMA controller, otherwise that byte could appear as the first byte of the next received frame.
FCR - FIFO Control Register Write Only
Used to enable the FIFOs, clear the FIFOs and set the interrupt threshold levels.
Upon reset, all bits are set to 0.
B3
B4
B5
B6
B7
Bits
Function
Reset State
B0
B1
B2
B3
B5-4
MIR, FIR Modes
FIFO_EN - Enable FIFOs.
When set to 1, both TX_FIFO and RX_FIFO are enabled.
In MIR, FIR and CEIR modes, the FIFOs are always enabled, and the setting of this bit is ignored.
RXSR - Receiver Soft Reset.
Writing a 1 to this bit position generates a receiver soft reset, whereby the receiver logic as well as the RX_FIFO
are both cleared.
This bit is automatically cleared by the hardware.
TXSR - Transmitter Soft Reset.
Writing a 1 to this bit position generates a transmitter soft reset, whereby the transmitter logic as well as the
TX_FIFO are both cleared.
This bit is automatically cleared by the hardware.
Reserved.
Write 0.
TXFTH [1-0] - TX-FIFO Interrupt Threshold.
In non-extended mode, these bits have no effect, regardless of the values written into them.
In extended mode, these bits select the TX_FIFO interrupt threshold level.
An interrupt is generated when the TX_FIFO level drops below the threshold.
Read as 0.
DMA_EV - DMA Event.
When an 8237 type DMA controller is used, this bit is set to 1 when a DMA terminal count (TC) is signaled.
It is cleared upon read.
This bit is the same as bit 6 of the LSR register. It is set to 1 when the transmitter is empty.
SFIF_EV - ST_FIFO Event.
Set to 1 when the ST_FIFO level is equal to or above the threshold, or an ST_FIFO time-out occurs.
This bit is cleared when the CPU reads the
ST_FIFO and its level drops below the threshold.
TMR_EV - Timer Event.
Set to 1 when the timer reaches 0.
Cleared by writing 1 into bit 7 of the ASCR register.
Reserved.
TXEMP_EV - Transmitter Empty.
RXFTH1
B7
0
Bits 5-4
RXFTH0
00
01
10
11
B6
0
TXFTH1
Figure 3-5. FIFO Control Register
B5
0
TX_FIFO Thresh.
(16 Levels)
13
TXFTH0
1
3
9
20
B4
0
res
B3
0
TX_FIFO Thresh.
(32 Levels)
17
25
TXSR
1
7
B2
0
RXSR
B1
0
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FIFO_EN
B0
0