PC87109VBE Nuvoton Technology Corporation of America, PC87109VBE Datasheet - Page 44

• Manufacturer Part Number: PC87109VBE
• Description: IC CONTROLLER ADV UART 32-LQFP
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of PC87109VBE

• Features: Transmit Deferral
• Number Of Channels: 2, DUART
• Fifo's: 16 Byte
• Voltage - Supply: 5V
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *PC87109VBE

Function
Reset State
4.0
4.1 Overview
On power-up or after a hardware reset, the PC87109 will have all of its modules and functions disabled.
The ID/IRSL [1-0] pins are in input mode. The IRTX and the UART output pin are set to their inactive state. Before normal
operation can be started, the device must be enabled and several items must be configured. These include the enabling and
polarity selection of the interrupt and DMA control signals.
Additional items, related to the communications protocols and the infrared transceiver interface, are configured via appropriate
registers in the UIR module register set.
4.2 Configuration Registers
Three registers are provided to control the basic configuration. One additional register is provided for device identification.
The PC87109 has a linear address space. The selected register bank occupies address locations at offsets 0 to 7. The
configuration registers are accessible at offsets 08h to 0Dh. A total of 12 locations are used. The four locations at offsets 0Bh,
0Ch, 0Eh and 0Fh are reserved.
The configuration registers and their corresponding offset values are shown in Table 4.1. A description of these registers is
provided in the following sections.
4.2.1 CSCFG – Control Signals Configuration Register (offset = 08h)
This register controls the configuration of the IRQ and DMA handshake signals as well as the selection of the register banks.
Bits
B2
B3
B1-0
Device Configuration
Reserved .
Read/write as 0.
EN_BNK -- Enable Register Banks.
When set to 1, any bank from 0 to 7 can be selected.
When this bit is cleared, only banks 0 and 1 can be selected, and any attempt to select banks 2 to 7 is ignored.
IRQINV – IRQ Polarity Invert.
When set to 1, the IRQ output signal polarity is inverted.
Value
TCINV
0
1
B7
0
Offset
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
08h
09h
Active High
Active Low
IRQ Signal
DACKINV
B6
0
Figure 4-1. Control Signals Configuration Register
CSCFG
CSEN
MCTL
Reserved
Reserved
DID
Reserved
Reserved
Register
DRQINV
Table 4-1. Configuration Registers
B5
0
Control Signals Configuration Register
Control Signals Enable Register
Mode Control Register
Device Identification Register
IRQBC
B4
44
0
Description
IRQINV
B3
0
EN_BNK
B2
0
res
B1
0
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res
B0
0