PC87109VBE Nuvoton Technology Corporation of America, PC87109VBE Datasheet - Page 13

• Manufacturer Part Number: PC87109VBE
• Description: IC CONTROLLER ADV UART 32-LQFP
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of PC87109VBE

• Features: Transmit Deferral
• Number Of Channels: 2, DUART
• Fifo's: 16 Byte
• Voltage - Supply: 5V
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *PC87109VBE

transmission, start, stop and parity bits are not included in
the transmitted data stream. Logic 1 in the bit string will
keep the LED off, so no infrared signal is transmitted. A
logic 0 will generate a sequence of modulating pulses
which will turn on the transmitter LED. Frequency and pulse
width of the modulating pulses are programmed by the
MCFR and MCPW bits in the IRTXMC register as well as
the TXHSC bit in the RCCFG register.
The RC_MMD bits select the transmitter modulation mode.
generated continuously for the entire time in which one or
more logic 0 bits are being transmitted. If 6_PLS or 8_PLS
modes are selected, 6 or 8 pulses are generated each time
one or more logic 0 bits are transmitted following logic 1 bit.
RCA protocols. 8_PLS or 6_PLS modulation mode is used
for the RECS 80 protocol. The 8_PLS or 6_PLS mode
allows minimization of the number of bits needed to
represent the RECS 80 infrared code sequence. The
current transmitter implementation supports only the
modulated modes of the RECS 80 protocol. The flash
mode is not supported since it is not popular and is
becoming less frequently used.
Note: The total transmission time for the logic 0 bits must
be equal or greater than 6 or 8 times the period of the
modulation sub-carrier, otherwise fewer pulses will be
transmitted.
2.6.2 Consumer Electronics IR Receive
The CEIR receiver is significantly different from a UART
receiver for two basic reasons. First, the incoming infrared
signals are DASK modulated. Therefore, a demodulation
operation may be necessary. Second, there are no start
bits in the incoming data stream.
Whenever an infrared signal is detected, the operations
performed by the receiver are slightly different depending
on whether or not receiver demodulation is enabled. If the
demodulator is not enabled, the receiver will immediately
switch to the active state. If the demodulator is enabled, the
receiver checks the sub-carrier frequency of the incoming
signal, and it switches to the active state only if the
frequency falls within the programmed range. If this is not
the case, the signal is ignored and no other action is taken.
When the receiver active state is entered, the RXACT bit in
the ASCR register is set to 1. Once in the active state, the
receiver keeps sampling the infrared input signal and
generates a bit streams where logic 1 indicates an idle
condition and logic 0 indicates the presence of infrared
energy. The infrared input is sampled regardless of the
presence of infrared pulses at a rate determined by the
value loaded into the baud generator divisor register. The
received bit string is both de-serialized and assembled into
8-bit characters, or it is converted to run-length encoding
values. The resulting data bytes are then transferred to the
RX_FIFO.
The receiver also sets the RXWDG bit in the ASCR register
each time an infrared pulse signal is detected. This bit is
automatically cleared when the ASCR register is read, and
it is intended to assist the software in determining when the
infrared link has been idle for a certain time. The software
can then stop the data reception by writing a 1 into the
If C_PLS mode is selected, modulation pulses are
C_PLS modulation mode is used for RC-5, RC-6, NEC and
13
RXACT bit to clear it and return the receiver to the inactive
state.
The frequency bandwidth for the incoming modulated
infrared signal is selected by DFR and DBW bits in the
IRRXDC register. There are two CEIR receiver data
modes: "Over-sampled" and "Programmed-T-Period"
mode. For either mode the sampling rate is determined by
the setting of the baud generator divisor register.
The "Over-sampled" mode can be used with the receiver
demodulator either enabled or disabled. It should be used
with the demodulator disabled when a detailed snapshot of
the incoming signal is needed, for example to determine the
period of the sub-carrier signal. If the demodulator is
enabled, the stream of samples can be used to reconstruct
the incoming bit string. To obtain a good resolution, a fairly
high sampling rate should be selected.
The "Programmed-T-Period" mode should be used with the
receiver demodulator enabled. The T Period represents
one half bit time, for protocols using bi-phase encoding, or
the basic unit of pulse distance, for protocols using pulse
distance encoding. The baud rate is usually programmed to
match the T Period. For long periods of logic low or high,
the receiver samples the demodulated signal at the
programmed sampling rate.
Whenever a new infrared energy pulse is detected, the
receiver will re-synchronize the sampling process to the
incoming signal timing. This reduces timing related errors
and eliminates the possibility of missing short infrared pulse
sequences, especially when dealing with the RECS 80
protocol. In addition, the "Programmed-T-Period" sampling
minimizes the amount of data used to represent the
incoming infrared signal, therefore reducing the processing
overhead in the host CPU.
2.7 FIFO Time-outs
In order to prevent received data from sitting in the RX
_FIFO and/or the ST_FIFO indefinitely, if the programmed
interrupt or DMA thresholds are not reached, time-out
mechanisms are provided.
An RX_FIFO time-out generates a receiver High-Data-
Level interrupt and/or a Receiver DMA request if bit 0 of
IER and/or bit 2 of MCR (in extended mode) are set to 1
respectively. An RX_FIFO time-out also sets bit 0 of ASCR
to 1 if the RX_FIFO is below the threshold. This bit is
tested by the software, when a receiver High-Data-Level
interrupt occurs, to decide whether a number of bytes, as
indicated by the RX_FIFO threshold, can be read without
checking bit 0 of the LSR register. An ST_FIFO time-out is
enabled only in MIR and FIR modes, and generates an
interrupt if bit 6 of IER is set to 1.
The conditions that must exist for a time-out to occur in the
various modes of operation are described below. When a
time-out has occurred, it can only be reset when the CPU
or DMA controller reads the FIFO that caused the time-out.
MIR or FIR Modes
RX_FIFO Time-out Conditions:
1.
2.
At least one byte is in the RX_FIFO, and
More than 64 s have elapsed since the last byte
was loaded into the RX_FIFO from the receiver logic,
and
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