PC87109VBE Nuvoton Technology Corporation of America, PC87109VBE Datasheet - Page 25

• Manufacturer Part Number: PC87109VBE
• Description: IC CONTROLLER ADV UART 32-LQFP
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of PC87109VBE

• Features: Transmit Deferral
• Number Of Channels: 2, DUART
• Fifo's: 16 Byte
• Voltage - Supply: 5V
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *PC87109VBE

3.1.7 SPR/ASCR - Scratchpad/Auxiliary Status and Control Register
These registers share the same address.
SPR - Scratchpad Register.
This register is accessed when the device is in non-extended mode.
It is to be used by the programmer to hold data temporarily and it has no control the device in any way.
B4
B5
B6
B7
MIR Mode
FIR Mode
UART, Sharp-IR, SIR Modes
MIR, FIR Modes
UART, Sharp-IR, SIR Modes
MIR, FIR Modes
PHY_ERR - Physical Layer Error.
Set to 1 when an abort condition is detected during the reception of a frame, and the last byte of the frame has
reached the bottom of the RX_FIFO.
PHY_ERR - Physical Layer Error.
Set to 1 when an encoding error or the sequence BOF-data-BOF is detected (missing EOF) during the reception of
a frame and the last byte of the frame has reached the bottom of the RX_FIFO.
Cleared upon read.
BRK - Break Event Detected.
Set to 1 when a sequence of logic 0 bits, equal or longer than a full character transmission, is received.
If the FIFOs are enabled, the Break condition will be associated with the particular character in the RX_FIFO it
applies to.
In which case, the BRK bit is set when the character reaches the bottom of the RX_FIFO. When a Break occurs
only one zero character is transferred to the receiver holding register or to the RX_FIFO.
The next character transfer takes place after at least one bit (logic 1) is received followed by a valid start bit.
Cleared upon read.
MAX_LEN - Maximum Length.
Set to 1 when a frame exceeding the maximum length has been received, and the last byte of the frame has
reached the bottom of the RX_FIFO.
Cleared upon read.
TXRDY - Transmitter Ready.
This bit is set to 1 when the Transmitter Holding Register or the TX_FIFO is empty.
It is cleared when a data character is written to the TXD port.
TXEMP - Transmitter Empty.
Set to 1 when the Transmitter is empty.
The transmitter empty condition occurs when the Holding Register or the TX_FIFO is empty, and the transmitter
front-end is idle.
ER_INF - Error in RX_FIFO.
Set to 1 when at least one character with a PE, FE or BRK condition is in the RX_FIFO.
This bit is always 0 in 16450 mode.
FR_END - Frame End. Set to 1 when the last byte (Frame End byte) of a received frame reaches the bottom of
the RX_FIFO.
Cleared upon read.
Cleared upon read.
25
www.national.com