PC87109VBE Nuvoton Technology Corporation of America, PC87109VBE Datasheet - Page 31

• Manufacturer Part Number: PC87109VBE
• Description: IC CONTROLLER ADV UART 32-LQFP
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of PC87109VBE

• Features: Transmit Deferral
• Number Of Channels: 2, DUART
• Fifo's: 16 Byte
• Voltage - Supply: 5V
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *PC87109VBE

3.3.5 TXFLV - TX_FIFO Level, Read Only
This register returns the number of bytes in the TX_FIFO. It can be used for software debugging or during recovery from a
transmitter under-run condition in one of the high-speed infrared modes.
3.3.6 RXFLV - RX_FIFO Level, Read Only
This register returns the number of bytes in the RX_FIFO. It can be used for software debugging.
3.4 Bank 3
3.4.1 MRID - Module Revision Identification Register, Read Only
When read, it returns the UART and Infrared (UIR) module identification and revision.
The returned value is 3Xh.
3.4.2 SH_LCR - Link Control Register Shadow, Read Only
This register returns the value of the LCR register.
The LCR register is written into when a byte value with bit 7 set to 0 is written to the LCR/BSR registers location (at offset 3)
from any bank.
B7
Bits
Function
Default
B5-0
B7-6
Bits
Function
Reset State
B5-0
B7-6
Return 0's.
RFL [5-0] - Number of bytes in RX_FIFO.
Reserved.
Return 0's.
TFL [5-0] - Number of bytes in TX_FIFO.
Reserved.
LOCK - Lock Bit.
When set to 1, accesses to the baud generator divisor register through LBGDL and LBGDH as well as fallback are
disabled from non-extended mode.
In this case two scratchpad registers overlaid with LBGDL and LBGDH are enabled, and any attempted CPU
access of the baud generator divisor register through LBGDL and LBGDH will access the scratchpad registers
instead. This bit must be set to 0 when extended mode is selected.
res
res
B7
B7
0
0
Address
Offset
4 - 7
0
1
2
3
res
res
B6
B6
0
0
MRID
SH_LCR
SH_FCR
LCR/BSR
Reserved
Register
Name
Figure 3-14. Transmit FIFO Level
Figure 3-15. Receive FIFO Level
RFL5
Table 3-9. Bank 3 Register Set
TFL5
B5
B5
0
0
Module Identification Register
Link Control Register Shadow
FIFO Control Register Shadow
Link Control/Bank Select Registers
RFL4
TFL4
31
B4
B4
0
0
Description
RFL3
TFL3
B3
B3
0
0
TFL2
RFL2
B2
B2
0
0
TFL1
RFL1
B1
B1
0
0
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TFL0
RFL0
B0
B0
0
0