PC87109VBE Nuvoton Technology Corporation of America, PC87109VBE Datasheet - Page 34

• Manufacturer Part Number: PC87109VBE
• Description: IC CONTROLLER ADV UART 32-LQFP
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of PC87109VBE

• Features: Transmit Deferral
• Number Of Channels: 2, DUART
• Fifo's: 16 Byte
• Voltage - Supply: 5V
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *PC87109VBE

3.6.1 LCR/BSR - Link Control/Bank Select Registers
These registers are the same as in bank 0.
3.6.2 IRCR2 - Infrared Control Register 2
Upon reset, the content of this register is 02h.
3.6.3 ST_FIFO - Status FIFO
The ST_FIFO is used in MIR and FIR Modes.
It is an 8-level FIFO and is intended to support back-to-back incoming frames in DMA mode, when an 8237-type DMA controller
is used. Each ST_FIFO entry contains both status information and frame length for a single frame, or the number of lost frames.
The bottom entry spans three address locations, and is accessed via the FRM_ST, RFRLL/LSTFRC and RFRLH registers. The
ST_FIFO is flushed when a hardware reset occurs or when the receiver is soft reset.
Note: The status and length information of received frames is loaded into the ST_FIFO whenever the DMA_EN bit in the
Bits
Function
Reset State
B0
B1
B2
B4
B5
B6
B7
B3
extended-mode MCR register is set to 1 and an 8237 type DMA controller is used. It is done regardless of whether the
CPU or the DMA controller is transferring the data from the RX_FIFO to memory. This implies that, during testing, if
full duplex is enabled and a DMA channel is servicing the transmitter while the CPU is servicing the receiver, the CPU
must still read the ST_FIFO otherwise it fills up and incoming frames will be rejected.
IR_FDPLX - Infrared Full Duplex Mode.
When set to 1, the infrared receiver is not masked during transmission.
Reserved.
Read/Write as 1.
MDRS - MIR Data Rate Select.
This bit determines the data rate in MIR mode.
0 => 1.152 Mbps
1 => 0.576 Mbps
TX_MS - Transmitter Mode Select.
This bit is used in MIR and FIR modes only.
When it is set to 1, transmitter frame-end stop mode is selected.
In this case the transmitter stops after transmission of a frame is complete, if the TFRCC counter reaching 0
generated the end-of-frame condition.
Clearing the TXHFE bit in the ASCR register can restart the transmitter.
AUX_IRRX – Auxiliary Infrared Input Select.
When set to 1, the infrared signal is received from the auxiliary input. See Table 3-17.
FEND_MD - Frame End Control.
This bit selects whether a terminal-count condition from the
TFRCC register will generate an EOF in PIO mode or DMA mode.
0 => TFRCC terminal count effective in PIO mode.
1 => TFRCC terminal count effective in DMA mode.
SFTSL - ST_FIFO Threshold Select.
An interrupt request is generated when the ST_FIFO level reaches the threshold or when an ST_FIFO timeout
occurs.
Reserved.
Read/write 0.
Bit Value
res
B7
0
1
0
Threshold Level
SFTSL
B6
0
2
4
Figure 3-17. Infrared Control Register 2
FEND_MD
B5
0
AUX_IRRX
34
B4
0
TX_MS
B3
0
MDRS
B2
0
res
B1
1
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IR_FDPLX
B0
0