PC87109VBE Nuvoton Technology Corporation of America, PC87109VBE Datasheet - Page 24

• Manufacturer Part Number: PC87109VBE
• Description: IC CONTROLLER ADV UART 32-LQFP
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of PC87109VBE

• Features: Transmit Deferral
• Number Of Channels: 2, DUART
• Fifo's: 16 Byte
• Voltage - Supply: 5V
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *PC87109VBE

Note: This register is intended for read operations only. Writing to this register is not recommended as it may cause
indeterminate results.
Bits
Function.
Reset State
B0
B1
B2
B3
UART, Sharp-IR, SIR, CEIR Modes
MIR, FIR Modes
UART, Sharp-IR, SIR Modes
MIR, FIR Modes
UART, Sharp-IR, SIR Modes
RXDA - Receiver Data Available.
Set to 1 when the Receiver Holding Register is full.
If the FIFOs are enabled, this bit is set when at least one character is in the RX_FIFO.
Cleared when the CPU reads all the data in the Holding Register or in the RX_FIFO.
OE - Overrun Error.
This bit is set to 1 as soon as the receiver detects an overrun condition.
Cleared upon read.
FIFOs Disabled:
FIFOs Enabled:
OE - Overrun Error.
An overrun occurs when a new character is completely received into the receiver front-end section and the
RX_FIFO or the ST_FIFO is full.
The new character is discarded, and the RX_FIFO is not affected.
Cleared upon read.
PE - Parity Error.
This bit is set to 1 if the received character did not have the correct parity, as selected by the parity control bits in
the LCR register.
If the FIFOs are enabled, the Parity Error condition will be associated with the particular character in the RX_FIFO
it applies to.
In which case, the PE bit is set when the character reaches the bottom of the RX_FIFO.
Cleared upon read.
BAD_CRC - CRC Error.
Set to 1 when a mismatch between the received CRC and the receiver-generated CRC is detected, and the last
byte of the received frame has reached the bottom of the RX_FIFO.
Cleared upon read.
FE - Framing Error.
This bit indicates that the received character did not have a valid stop bit.
It is set to 1 when the stop bit is detected as logic 0.
If the FIFOs are enabled, the Framing Error condition will be associated with the particular character in the
RX_FIFO it applies to.
In which case, the FE bit is set when the character reaches the bottom of the RX_FIFO.
After a Framing Error is detected, the receiver will try to re-synchronize.
If the bit following the stop bit position is 0, the receiver assumes it to be a valid start bit and the next character is
shifted in.
If that bit is 1, the receiver will enter the idle state looking for the next start bit.
Cleared upon read.
An overrun occurs when a new character is completely received into the receiver front-end section and the CPU
has not yet read the previous character in the receiver holding register. The new character is discarded, and the
receiver holding register is not affected.
An overrun occurs when a new character is completely received into the receiver front-end section and the
RX_FIFO is full.
The new character is discarded, and the RX_FIFO is not affected.
FR_END
ER_INF/
B7
0
TXEMP
B6
1
TXRDY
Figure 3-9. Link Status Register
B5
1
MAX_LEN
BRK/
B4
24
0
PHY_ERR
FE/
B3
0
BAD_CRC
PE/
B2
0
OE
B1
0
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RXDA
B0
0