PC87109VBE Nuvoton Technology Corporation of America, PC87109VBE Datasheet - Page 33

• Manufacturer Part Number: PC87109VBE
• Description: IC CONTROLLER ADV UART 32-LQFP
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of PC87109VBE

• Features: Transmit Deferral
• Number Of Channels: 2, DUART
• Fifo's: 16 Byte
• Voltage - Supply: 5V
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *PC87109VBE

3.5.3 LCR/BSR - Link Control/Bank Select Registers
These Registers are the same as in bank 0.
3.5.4 TFRL/TFRCC - Transmitter Frame-Length/Current-Count
These registers share the same addresses. TFRL is always accessed during write cycles and is used to program the frame
length, in bytes, for the frames to be transmitted. The frame length value does not include any appended CRC bytes. TFRL is
accessed during read cycles if the CTEST bit is set to 1, and returns the previously programmed value. Values from 1 to 2
can be used. The zero value is reserved and must not be used. TFRCC is loaded with the content of TFRL when transmission of
a frame begins, and decrement after each byte is transmitted. It is read-only and is accessed during CPU read cycles when the
CTEST bit is 0. It returns the number of currently remaining bytes of the frame being transmitted. These registers are 13 bits
wide and are split into two independently accessible parts occupying consecutive address locations. TFRLL and TFRCCL are
located at the lower address and access the least significant 8 bits, whereas TFRLH and TFRCCH are located at the higher
address and access the most significant 5 bits. To properly program TFRL, the CPU must always write the lower value into
TFRLL first and then the upper value into TFRLH. The upper 3 bits of TFRLH are reserved and must be written with 0's. In order
for a read access of TFRCC to return an accurate value, the CPU should always read TFRCCL first, and then TFRCCH. After
reset, the content of the TFRL register is 800h.
3.5.5 RFRML/RFRCC - Receiver Frame Maximum-Length/Current-Count
These registers share the same addresses. RFRML is always accessed during write cycles and is used to program the
maximum frame length, in bytes, for the frames to be received. The maximum frame length value includes the CRC bytes.
RFRML is accessed during read cycles if the CTEST bit is set to 1, and returns the previously programmed value. Values from 4
to 2
incoming frame, and an increment after each byte is received. It is read-only and is accessed during CPU read cycles when the
CTEST bit is 0. These registers are 13 bits wide and are split into two independently accessible parts occupying consecutive
address locations. RFRMLL and RFRCCL are located at the lower address and access the least significant 8 bits, whereas
RFRMLH and RFRCCH are located at the higher address and access the most significant 5 bits. To properly program RFRML,
the CPU must always write the lower value into RFRMLL first and then the upper value into RFRMLH. The upper 3 bits of
RFRMLH are reserved and must be written with 0's. In order for a read access of RFRCC to return an accurate value, the CPU
should always read RFRCCL first, and then RFRCCH. After reset, the content of the RFRML register is 800h.
Note: TFRCC and RFRCC are intended for testing purposes only. Use of these registers for any other purpose is not
3.6 Bank 5
B3-2
B7-4
13
- 1 can be used. The values from 0 to 3 are reserved and must not be used. RFRCC holds the current byte count of the
recommended.
IR_SL [1-0] - SIR or Sharp-IR Select, Non-Extended Mode Only.
These bits are used to select the appropriate infrared mode when the device is in non-extended mode.
They are ignored when extended mode is selected.
Reserved.
Write as 0’s.
Bits 3-2
Address
Offset
00
01
10
11
0-2
3
4
5
6
7
Reserved
LCR/BSR
IRCR2
FRM_ST
RFRLL/
LSTFRC
RFRLH
Register
Name
Selected Mode
UART
Reserved
Sharp-IR
SIR
Link Control/Bank Select Registers
Infrared Control Register 2
Frame Status
Received Frame Length Low-Byte /
Lost Frame Count
Received Frame Length High Byte
Table 3-11. Bank 5 Register Set
33
Description
www.national.com
13
- 1