PC87109VBE Nuvoton Technology Corporation of America, PC87109VBE Datasheet - Page 14

• Manufacturer Part Number: PC87109VBE
• Description: IC CONTROLLER ADV UART 32-LQFP
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of PC87109VBE

• Features: Transmit Deferral
• Number Of Channels: 2, DUART
• Fifo's: 16 Byte
• Voltage - Supply: 5V
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *PC87109VBE

UART, Sharp-IR, SIR Modes
CEIR Mode
2.8 Transmit Deferral
This feature allows the software to send short high-speed
data frames in PIO mode without the risk of a transmitter
under-run being generated. Even though this feature is
available and works the same way in all modes, it will most
likely be used in MIR and FIR modes to support high-speed
negotiations. This is because in other modes, either the
transmit data rate is relatively low and thus the CPU can
keep up with it without letting an under-run occur, as in the
case CEIR Mode, or transmit under-runs are allowed and
are not considered to be error conditions.
Transmit deferral is available only in extended mode and
when the TX_FIFO is enabled. When transmit deferral is
enabled (TX_DFR bit of MCR set to 1) and the transmitter
becomes empty, an internal flag will be set that locks the
transmitter. If the CPU now writes data into the TX_FIFO,
the transmitter will not start sending the data until the
TX_FIFO level reaches either 14 for a 16-level TX_FIFO, or
30 for a 32-level TX_FIFO, at which time the internal flag is
cleared. The internal flag is also cleared and the
transmitter starts transmitting when a time-out condition is
reached. This prevents some bytes from being in the
TX_FIFO indefinitely if the threshold is not reached.
A timer that is enabled when the internal flag is set and
there is at least one byte in the TX_FIFO implements the
time-out mechanism. Whenever a byte is loaded into the
TX_FIFO the timer gets reloaded with the initial value. If no
3.
ST_FIFO Time-out Conditions:
1.
2.
3.
RX_FIFO Time-out Conditions:
1.
2.
3.
RX_FIFO Time-out Conditions:
The RX_FIFO Time-out, in CEIR mode, is disabled while
the receiver is active. The conditions for this time-out to
occur are as follows:
1.
2.
3.
More than 64 s have elapsed since the last byte
was read from the RX_FIFO by the CPU or DMA
controller.
At least one entry is in the ST_FIFO, and
More than 1 ms has elapsed since the last byte was
loaded into the RX_FIFO from the receiver logic, and
More than 1 ms has elapsed since the CPU read the
last entry from the ST_FIFO.
At least one byte is in the RX_FIFO, and
More than four character times have elapsed since
the last byte was loaded into the RX_FIFO from the
receiver
More than four character times have elapsed since
the last byte was read from the RX_FIFO by the CPU
or DMA controller.
At least one byte has been in the RX_FIFO for 64 s
or more, and
The receiver has been inactive (RXACT=0) for 64 s
or more, and
More than 64 s have elapsed since the last byte
was read from the RX_FIFO by the CPU or DMA
controller.
logic, and
14
bytes are loaded for a 64 s time, the timer times out and
the internal flag gets cleared, thus enabling the transmitter.
2.9 Automatic Fallback to 16550
Compatibility Mode
This feature is designed to support existing legacy software
packages using the 16550 UART.
For proper operation, many of these software packages
require that the device look identical to a plain 16550 since
they access the UART registers directly.
Due to the fact that several extended features as well as
new operational modes are provided, the user must make
sure that the device is in the proper state before a legacy
program can be executed.
The fallback mechanism is designed for this purpose. It
eliminates the need for user intervention to change the
state of the device, when a legacy program must be
executed following completion of a program that used any
of the device’s extended features.
This mechanism automatically switches the device to
16550 compatibility mode and turns off any extended
features whenever the baud generator divisor register is
accessed through the LBGDL or LBGDH ports in register
bank 1.
In order to avoid spurious fallbacks, baud generator divisor
ports are provided in bank 2. Accesses of the baud
generator divisor through these ports will change the baud
rate setting but will not cause a fall back.
New programs, designed to take advantage of the device
extended features, should not use LBGDL and LBGDH to
change the baud rate. They should use the BGDL or
BGDH instead.
A fallback can occur from either extended or non-extended
modes. If extended mode is selected, fallback is always
enabled. In this case, when a fallback occurs, the following
happens:
1.
2.
3.
4.
5.
When a fallback occurs from non-extended mode, only the
first three of the above actions will take place. No switching
to UART mode occurs if either Sharp-IR or SIR infrared
modes were selected. This prevents spurious switching to
UART mode when a legacy program, running in infrared
mode, accesses the baud generator divisor register from
bank 1.
Setting the LOCK bit in the EXCR2 register can disable
fallback from non-extended mode. When Lock is set to 1
and the device is in non-extended mode, two scratch-pad
registers overlaid with LBGDL and LBGDH are enabled.
Any attempted CPU access of the baud generator divisor
register through LBGDL and LBGDH will access the
scratch-pad registers, and the baud rate setting will not be
affected. This feature allows existing legacy programs to
run faster than 115.2 Kbaud without their being aware of it.
Transmitter and receiver FIFOs will switch to 16 levels.
A value of 13 will be selected for the baud generator
prescaler.
The ETDLBK and BTEST bits in the EXCR1 Register
will be cleared.
UART mode will be selected.
A switch to non-extended mode will occur.
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