PC87109VBE Nuvoton Technology Corporation of America, PC87109VBE Datasheet - Page 45

• Manufacturer Part Number: PC87109VBE
• Description: IC CONTROLLER ADV UART 32-LQFP
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of PC87109VBE

• Features: Transmit Deferral
• Number Of Channels: 2, DUART
• Fifo's: 16 Byte
• Voltage - Supply: 5V
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *PC87109VBE

Function
Reset State
Function
Reset State
4.2.2 CSEN - Control Signals Enable Register (offset = 09h)
This register is used to enable the Interrupt output signal, and the DMA control signals for the device's receiver and transmitter
communication channels.
Bits
4.2.3 MCTL - Mode Control Register (offset = 0Ah)
This register is used to enable the device and select the power mode.
It also returns the device's busy/Idle state.
Bits
B4
B5
B6
B7
B0
B1-2
B3
B4-7
When this bit is set to 1, the interrupt output signal is enabled.
IRQ_EN -- IRQ Signal Enable.
After reset, this bit is cleared, and the IRQ output pin is in TRI-STATE condition.
Reserved.
Reserved.
IRQBC -- IRQ Output Buffer Configuration.
This bit determines whether the IRQ output buffer is configured as Open Drain or Totem Pole.
DRQINV – DRQ Polarity Invert.
When set to 1, the DRQ output signal polarity is inverted.
DACKINV – DACK Polarity Invert.
When set to 1, the DACK input signal polarity is inverted.
TCINV – TC Polarity Invert.
When set to 1, the TC input signal polarity is inverted.
Read/Write as 0.
DCH_EN -- DMA Control Signals Enable.
When this bit is set to 1, the DMA control signals are enabled and are routed to either the internal receiver or the
internal transmitter DMA channel depending on the setting of the DMASWP bit in the EXCR1 register.
After reset, this bit is cleared, and the DMA control signals are disabled; DRQ is floated, DACK and TC are blocked.
Read/Write as 0.
Value
Value
Value
Value
0
0
0
0
1
1
1
1
res
B7
B7
res
0
0
Output Buffer Type
Active High
Active Low
Active High
Active Low
Active High
Active Low
DRQ Signal
DRQ Signal
TC Signal
Open Drain
Totem Pole
B6
res
B6
res
0
0
Figure 4-2. Control Signals Enable Register
Figure 4-3. Mode Control Register
Res
res
B5
B5
0
0
res
B4
B4
res
45
0
0
DCH_EN
B3
B3
res
0
0
BUSY
res
B2
B2
0
0
NOM
res
B1
B1
0
0
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IRQ_EN
DEV_EN
B0
B0
0
0