AT91SAM9G45-EKES Atmel, AT91SAM9G45-EKES Datasheet - Page 1109
AT91SAM9G45-EKES
Manufacturer Part Number
AT91SAM9G45-EKES
Description
KIT EVAL FOR AT91SAM9G45
Manufacturer
Atmel
Series
AT91SAM Smart ARMr
Type
MCUr
Datasheets
1.AT91SAM9G45-EKES.pdf
(56 pages)
2.AT91SAM9G45-EKES.pdf
(1218 pages)
3.AT91SAM9G45-EKES.pdf
(66 pages)
Specifications of AT91SAM9G45-EKES
Contents
Board
Processor To Be Evaluated
SAM9G45
Data Bus Width
32 bit
Interface Type
I2C, SPI, UART
Maximum Operating Temperature
+ 50 C
Minimum Operating Temperature
- 10 C
Operating Supply Voltage
1.8 V to 3.3 V
For Use With/related Products
AT91SAM9G45
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
Q4626953
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Figure 45-4. Full Frame Timing, MMODE=0
6438F–ATARM–21-Jun-10
The LCDDOTCK signal is used to clock the data into the LCD drivers' shift register. The data is
sent through LCDD[23:0] synchronized by default with LCDDOTCK falling edge (rising edge can
be selected). The CLKVAL field of LCDCON1 register controls the rate of this signal. The divisor
can also be bypassed with the BYPASS bit in the LCDCON1 register. In this case, the rate of
LCDDOTCK is equal to the frequency of the LCDC Core clock. The minimum period of the LCD-
DOTCK signal depends on the configuration. This information can be found in
The LCDDOTCK signal has two different timings that are selected with the CLKMOD field of the
LCDCON2 register:
Table 45-14. Minimum LCDDOTCK Period in LCDC Core Clock Cycles
The LCDDEN signal indicates valid data in the LCD Interface.
After each horizontal line of data has been shifted into the LCD, the LCDHSYNC is asserted to
cause the line to be displayed on the panel.
The following timing parameters can be configured:
DISTYPE
TFT
STN Mono
STN Mono
STN Mono
STN Mono
STN Color
STN Color
STN Color
STN Color
• Always Active (used with TFT LCD Modules)
• Active only when data is available (used with STN LCD Modules)
LCDDOTCK
LCDMOD
LCDVSYNC
f
LCDDOTCK
Line1
Line2
Line3
SCAN
Single
Single
Dual
Dual
Single
Single
Dual
Dual
=
Line4
------------------------------- -
CLKVAL
Configuration
f
LCDC_clock
Line5
+
1
IFWIDTH
4
8
8
16
4
8
8
16
AT91SAM9G45
LCDDOTCK Period
1
4
8
8
16
2
2
4
6
Table
45-14.
1109
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