AT91SAM9G45-EKES Atmel, AT91SAM9G45-EKES Datasheet - Page 1112
AT91SAM9G45-EKES
Manufacturer Part Number
AT91SAM9G45-EKES
Description
KIT EVAL FOR AT91SAM9G45
Manufacturer
Atmel
Series
AT91SAM Smart ARMr
Type
MCUr
Datasheets
1.AT91SAM9G45-EKES.pdf
(56 pages)
2.AT91SAM9G45-EKES.pdf
(1218 pages)
3.AT91SAM9G45-EKES.pdf
(66 pages)
Specifications of AT91SAM9G45-EKES
Contents
Board
Processor To Be Evaluated
SAM9G45
Data Bus Width
32 bit
Interface Type
I2C, SPI, UART
Maximum Operating Temperature
+ 50 C
Minimum Operating Temperature
- 10 C
Operating Supply Voltage
1.8 V to 3.3 V
For Use With/related Products
AT91SAM9G45
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
Q4626953
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Figure 45-6. TFT Panel Timing, CLKMOD = 0, VPW = 2, VBP = 2, VFP = 1
Figure 45-7. TFT Panel Timing (Line Expanded View), CLKMOD = 1
1112
LCDHSYNC
LCDVSYNC
LCDHSYNC
LCDVSYNC
LCDDOTCK
LCDHSYNC
LCDDOTCK
LCDVSYNC
LCDDEN
LCDDOTCK
LCDDEN
LCDDEN
AT91SAM9G45
LCDD
LCDD
LCDD
VHDLY+1
VHDLY+1
Vertical Back Porch = VBP Lines
VHDLY+1
--------------------------- -
f
LCDVSYNC
Usually the LCD_FRM rate is about 70 Hz to 75 Hz. It is given by the following equation:
where:
In STN Mode:
1
• HOZVAL determines de number of LCDDOTCK cycles per line
• LINEVAL determines the number of LCDHSYNC cycles per frame, according to the
HPW+1
HPW+1
expressions shown below:
(VPW+1) Lines
=
VHDLY
------------------------------------------------------------------------------------------------------------------------- - VBP
HBP+1
HBP+1
HOZVAL
+
1 PCLK
1 PCLK
HPW
=
Horizontal_display_size
-------------------------------------------------------------- - 1
Line Period
+
Line Period
HBP
f
Number_data_lines
LCDDOTCK
Frame Period
1/2 PCLK 1/2 PCLK
+
1/2 PCLK 1/2 PCLK
HOZVAL
+
HOZVAL+1
HOZVAL+1
HFP
–
+
4
+
LINEVAL
Vertical Fron t Porch = VFP Lines
+
6438F–ATARM–21-Jun-10
VFP
HFP+VHDLY+2
HFP+VHDLY+2
+
1
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