AT91SAM9G45-EKES Atmel, AT91SAM9G45-EKES Datasheet - Page 302

• Manufacturer Part Number: AT91SAM9G45-EKES
• Description: KIT EVAL FOR AT91SAM9G45
• Manufacturer: Atmel
• Series: AT91SAM Smart ARMr
• Type: MCUr

Specifications of AT91SAM9G45-EKES

• Contents: Board
• Processor To Be Evaluated: SAM9G45
• Data Bus Width: 32 bit
• Interface Type: I2C, SPI, UART
• Maximum Operating Temperature: + 50 C
• Minimum Operating Temperature: - 10 C
• Operating Supply Voltage: 1.8 V to 3.3 V
• For Use With/related Products: AT91SAM9G45
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q4626953

25.2.1.3
25.3
25.4
302
Master Clock Controller
Processor Clock Controller
AT91SAM9G45
No UDP HS, UHP FS and DDR2 Mode
The Master Clock Controller provides selection and division of the Master Clock (MCK). MCK is
the clock provided to all the peripherals and the memory controller.
The Master Clock is selected from one of the clocks provided by the Clock Generator. Selecting
the Slow Clock provides a Slow Clock signal to the whole device. Selecting the Main Clock
saves power consumption of the PLLA.
The Master Clock Controller is made up of a clock selector and a prescaler. It also contains a
Master Clock divider which allows the processor clock to be faster than the Master Clock.
The Master Clock selection is made by writing the CSS field (Clock Source Selection) in
PMC_MCKR (Master Clock Register). The prescaler supports the division by a power of 2 of the
selected clock between 1 and 64. The PRES field in PMC_MCKR programs the prescaler. The
Master Clock divider can be programmed through the MDIV field in PMC_MCKR.
Note:
Each time PMC_MCKR is written to define a new Master Clock, the MCKRDY bit is cleared in
PMC_SR. It reads 0 until the Master Clock is established. Then, the MCKRDY bit is set and can
trigger an interrupt to the processor. This feature is useful when switching from a high-speed
clock to a lower one to inform the software when the change is actually done.
Figure 25-2. Master Clock Controller
The PMC features a Processor Clock Controller (PCK) that implements the Processor Idle
Mode. The Processor Clock can be disabled by writing the System Clock Disable Register
• Only PLLA is running at 384 MHz, UPLL power consumption is saved
• USB Device High Speed and Host EHCI High Speed operations are NOT allowed
• Full Speed OHCI input clock is PLLACK, USBDIV is 7 (division by 8)
• System Input clock is PLLACK, PCK is 384 MHz
• MDIV is ‘11’, MCK is 128 MHz
• DDR2 can be used at up to 128 MHz
MAINCK
UPLLCK
PLLACK
SLCK
It is forbidden to modify MDIV and CSS at the same access. Each field must be modified sepa-
rately with a wait for MCKRDY flag between the first field modification and the second field
modification.
PMC_MCKR
CSS
Master Clock
PMC_MCKR
Prescaler
PRES
PMC_MCKR
Processor
Master
Divider
Divider
Clock
Clock
MDIV
MCK
To the Processor
Clock Controller (PCK)
6438F–ATARM–21-Jun-10