AT91SAM9G45-EKES Atmel, AT91SAM9G45-EKES Datasheet - Page 1124

• Manufacturer Part Number: AT91SAM9G45-EKES
• Description: KIT EVAL FOR AT91SAM9G45
• Manufacturer: Atmel
• Series: AT91SAM Smart ARMr
• Type: MCUr

Specifications of AT91SAM9G45-EKES

• Contents: Board
• Processor To Be Evaluated: SAM9G45
• Data Bus Width: 32 bit
• Interface Type: I2C, SPI, UART
• Maximum Operating Temperature: + 50 C
• Minimum Operating Temperature: - 10 C
• Operating Supply Voltage: 1.8 V to 3.3 V
• For Use With/related Products: AT91SAM9G45
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q4626953

45.11 Register Configuration Guide
45.11.1
45.11.2
1124
AT91SAM9G45
STN Mode Example
TFT Mode Example
Program the PIO Controller to enable LCD signals.
Enable the LCD controller clock in the Power Management Controller.
STN color(R,G,B) 320*240, 8-bit single scan, 70 frames/sec, Master clock = 60 Mhz
Data rate: 320*240*70*3/8 = 2.016 MHz
HOZVAL= ((3*320)/8) - 1
LINEVAL= 240 -1
CLKVAL = (60 MHz/2.016 MHz) - 1 = 29
LCDCON1= CLKVAL << 12
LCDCON2 = LITTLEENDIAN | SINGLESCAN | STNCOLOR | DISP8BIT| PS8BPP;
LCDTIM1 = 0;
LCDTIM2 = 10 | (10 << 21);
LCDFRMCFG = (HOZVAL << 21) | LINEVAL;
LCDMVAL = 0x80000004;
DMAFRMCFG = (7 << 24) + (320 * 240 * 8) / 32;
This example is based on the NEC TFT color LCD module NL6448BC20-08
TFT 640*480, 16-bit single scan, 60 frames/sec, pixel clock frequency = [21MHz..29MHz] with a
typical value = 25.175 MHz.
The Master clock must be (n + 1)*pixel clock frequency
HOZVAL = 640 - 1
LINEVAL = 480 - 1
If Master clock is 100 MHz
CLKVAL = (100 MHz/ 25.175 MHz) - 1= 3
VFP = (12 -1), VBP = (31-1), VPW = (2-1), VHDLY= (2-1)
HFP = (16-1), HBP = (48 -1), HPW= (96-1)
LCDCON1= CLKVAL << 12
LCDCON2 = LITTLEENDIAN | CLKMOD | INVERT_CLK | INVERT_LINE | INVERT_FRM |
PS16BPP | SINGLESCAN | TFT
LCDTIM1 = VFP | (VBP << 8) | (VPW << 16) | (VHDLY << 24)
LCDTIM2 = HBP | (HPW << 8) | (HFP << 21)
LCDFRMCFG = (HOZVAL << 21) | LINEVAL
LCDMVAL = 0
DMAFRMCFG = (7 << 24) + (640 * 480* 16) / 32;
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6438F–ATARM–21-Jun-10