AT91SAM9G45-EKES Atmel, AT91SAM9G45-EKES Datasheet - Page 137

• Manufacturer Part Number: AT91SAM9G45-EKES
• Description: KIT EVAL FOR AT91SAM9G45
• Manufacturer: Atmel
• Series: AT91SAM Smart ARMr
• Type: MCUr

Specifications of AT91SAM9G45-EKES

• Contents: Board
• Processor To Be Evaluated: SAM9G45
• Data Bus Width: 32 bit
• Interface Type: I2C, SPI, UART
• Maximum Operating Temperature: + 50 C
• Minimum Operating Temperature: - 10 C
• Operating Supply Voltage: 1.8 V to 3.3 V
• For Use With/related Products: AT91SAM9G45
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q4626953

19.5.1.2
19.5.2
6438F–ATARM–21-Jun-10
Arbitration Priority Scheme
Slot Cycle Limit Arbitration
Use of undefined length 16-beat bursts or less is discouraged since this generally decreases
significantly overall bus bandwidth due to arbitration and slave latencies at each first access of a
burst.
If the master does not permanently and continuously request the same slave or has an intrinsi-
cally limited average throughput, the ULBT should be let at its default unlimited value, knowing
that the AHB specification natively limits all word bursts to 256 beats and double-word bursts to
128 beats because of its 1 Kilobyte address boundaries.
Unless duly needed the ULBT should be let to its default 0 value for power saving.
This selection can be done through the field ULBT of the Master Configuration Registers
(MATRIX_MCFG).
The Bus Matrix contains specific logic to break long accesses, such as back to back undefined
length bursts or very long bursts on a very slow slave (e.g., an external low speed memory). At
each arbitration time a counter is loaded with the value previously written in the SLOT_CYCLE
field of the related Slave Configuration Register (MATRIX_SCFG) and decreased at each clock
cycle. When the counter elapses, the arbiter has the ability to re-arbitrate at the end of the cur-
rent AHB bus access cycle.
Unless some master has a very tight access latency constraint which could lead to data overflow
or underflow due to a badly undersized internal fifo with respect to its throughput, the Slot Cycle
Limit should be disabled (SLOT_CYCLE = 0) or let to its default maximum value in order not to
inefficiently break long bursts performed by some ATMEL masters.
However, the Slot Cycle Limit should not be disabled in the very particular case of a master
capable of accessing the slave by performing back to back undefined length bursts shorter than
the number of ULBT beats with no Idle cycle in between, since in this case the arbitration could
be frozen all along the bursts sequence.
In most cases this feature is not needed and should be disabled for power saving.
Warning: This feature cannot prevent any slave from locking its access indefinitely.
The bus Matrix arbitration scheme is organized in priority pools.
Round-Robin priority is used inside the highest and lowest priority pools, whereas fix level prior-
ity is used between priority pools and inside the intermediate priority pools.
4. 8-beat bursts: Predicted end of burst is generated at the end of each 8-beat boundary
5. 16-beat bursts: Predicted end of burst is generated at the end of each 16-beat bound-
6. 32-beat bursts: Predicted end of burst is generated at the end of each 32-beat bound-
7. 64-beat bursts: Predicted end of burst is generated at the end of each 64-beat bound-
8. 128-beat bursts: Predicted end of burst is generated at the end of each 128-beat
inside INCR transfer.
ary inside INCR transfer.
ary inside INCR transfer.
ary inside INCR transfer.
boundary inside INCR transfer.
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