AT91SAM9G45-EKES Atmel, AT91SAM9G45-EKES Datasheet - Page 18

• Manufacturer Part Number: AT91SAM9G45-EKES
• Description: KIT EVAL FOR AT91SAM9G45
• Manufacturer: Atmel
• Series: AT91SAM Smart ARMr
• Type: MCUr

Specifications of AT91SAM9G45-EKES

• Contents: Board
• Processor To Be Evaluated: SAM9G45
• Data Bus Width: 32 bit
• Interface Type: I2C, SPI, UART
• Maximum Operating Temperature: + 50 C
• Minimum Operating Temperature: - 10 C
• Operating Supply Voltage: 1.8 V to 3.3 V
• For Use With/related Products: AT91SAM9G45
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q4626953

18
AT91SAM9G45
The control of these delays is the following:
DDR_D[15:0] controlled by 2 registers, DELAY1 and DELAY2, located in the DDRSDRC user
interface
DDR_A[13:0] controlled by 2 registers, DELAY3 and DELAY4, located in the DDRSDRC user
interface
D[15:0] controlled by 2 registers, DELAY1 and DELAY2, located in the HSMC3 user interface
D[31,16]on PIOC[31:16] controlled by 2 registers, DELAY3 and DELAY4, located in the
HSMC3 user interface
• DDRSDRC
• EBI (DDRSDRC\HSMC3\Nandflash)
– DDR_D[0] <=> DELAY1[3:0],
– DDR_D[1] <=> DELAY1[7:4],...
– DDR_D[6] <=> DELAY1[27:24],
– DDR_D[7] <=> DELAY1[31:28]
– DDR_D[8] <=> DELAY2[3:0],
– DDR_D[9] <=> DELAY2[7:4],...,
– DDR_D[14] <=> DELAY2[27:24],
– DDR_D[15] <=> DELAY2[31:28]
– DDR_A[0] <=> DELAY3[3:0],
– DDR_A[1] <=> DELAY3[7:4], ...,
– DDR_A[6] <=> DELAY3[27:24],
– DDR_A[7] <=> DELAY3[31:28]
– DDR_A[8] <=> DELAY4[3:0],
– DDR_A[9] <=> DELAY4[7:4], ...,
– DDR_A[12] <=> DELAY4[19:16],
– DDR_A[13] <=> DELAY4[23:20]
– D[0] <=> DELAY1[3:0],
– D[1] <=> DELAY1[7:4],...,
– D[6] <=> DELAY1[27:24],
– D[7] <=> DELAY1[31:28]
– D[8] <=> DELAY2[3:0],
– D[9] <=> DELAY2[7:4],...,
– D[14] <=> DELAY2[27:24],
– D[15] <=> DELAY2[31:28]
– D[16] <=> DELAY3[3:0],
– D[17] <=> DELAY3[7:4],...,
– D[22] <=> DELAY3[27:24],
– PC[23] <=> DELAY3[31:28]
6438F–ATARM–21-Jun-10