AT91SAM9G45-EKES Atmel, AT91SAM9G45-EKES Datasheet - Page 433

• Manufacturer Part Number: AT91SAM9G45-EKES
• Description: KIT EVAL FOR AT91SAM9G45
• Manufacturer: Atmel
• Series: AT91SAM Smart ARMr
• Type: MCUr

Specifications of AT91SAM9G45-EKES

• Contents: Board
• Processor To Be Evaluated: SAM9G45
• Data Bus Width: 32 bit
• Interface Type: I2C, SPI, UART
• Maximum Operating Temperature: + 50 C
• Minimum Operating Temperature: - 10 C
• Operating Supply Voltage: 1.8 V to 3.3 V
• For Use With/related Products: AT91SAM9G45
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q4626953

Figure 29-10. Programmable Delays
29.7.3.5
29.7.3.6
6438F–ATARM–21-Jun-10
Chip Select 1
Chip Select 2
SPI Peripheral DMA Controller (PDC)
Peripheral Selection
SPCK
These delays allow the SPI to be adapted to the interfaced peripherals and their speed and bus
release time.
The serial peripherals are selected through the assertion of the NPCS0 to NPCS3 signals. By
default, all the NPCS signals are high before and after each transfer.
Fixed Peripheral Select is activated by writing the PS bit to zero in SPI_MR (Mode Register). In
this case, the current peripheral is defined by the PCS field in SPI_MR and the PCS field in the
SPI_TDR has no effect.
Variable Peripheral Select is activated by setting PS bit to one. The PCS field in SPI_TDR is
used to select the current peripheral. This means that the peripheral selection can be defined for
each new data. The value to write in the SPI_TDR register as the following format.
[xxxxxxx(7-bit) + LASTXFER(1-bit)
equals to the chip select to assert as defined in
LASTXFER bit at 0 or 1 depending on CSAAT bit. CSAAT, LASTXFER and CSNAAT bit are dis-
cussed in the Peripheral Deselection in
Note:
In both fixed and variable mode the Peripheral DMA Controller (PDC) can be used to reduce
processor overhead.
The Fixed Peripheral Selection allows buffer transfers with a single peripheral. Using the PDC is
an optimal means, as the size of the data transfer between the memory and the SPI is either 8
bits or 16 bits. However, changing the peripheral selection requires the Mode Register to be
reprogrammed.
The Variable Peripheral Selection allows buffer transfers with multiple peripherals without repro-
gramming the Mode Register. Data written in SPI_TDR is 32 bits wide and defines the real data
to be transmitted and the peripheral it is destined to. Using the PDC in this mode requires 32-bit
wide buffers, with the data in the LSBs and the PCS and LASTXFER fields in the MSBs, how-
• Fixed Peripheral Select: SPI exchanges data with only one peripheral
• Variable Peripheral Select: Data can be exchanged with more than one peripheral without
having to reprogram the NPCS field in the SPI_MR register.
1. Optional.
DLYBCS
DLYBS
(1)
+ xxxx(4-bit) + PCS (4-bit) + DATA (8 to 16-bit)] with PCS
Section
Section 29.8.4
29.7.3.11.
DLYBCT
(SPI Transmit Data Register) and
AT91SAM9G45
DLYBCT
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