AT91SAM9G45-EKES Atmel, AT91SAM9G45-EKES Datasheet - Page 321

• Manufacturer Part Number: AT91SAM9G45-EKES
• Description: KIT EVAL FOR AT91SAM9G45
• Manufacturer: Atmel
• Series: AT91SAM Smart ARMr
• Type: MCUr

Specifications of AT91SAM9G45-EKES

• Contents: Board
• Processor To Be Evaluated: SAM9G45
• Data Bus Width: 32 bit
• Interface Type: I2C, SPI, UART
• Maximum Operating Temperature: + 50 C
• Minimum Operating Temperature: - 10 C
• Operating Supply Voltage: 1.8 V to 3.3 V
• For Use With/related Products: AT91SAM9G45
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q4626953

25.11.10 PMC Clock Generator PLLA Register
Register Name:CKGR_PLLAR
Address:
Access Type:Read/Write
Possible limitations on PLL input frequencies and multiplier factors should be checked before using the PMC.
Warning: Bit 29 must always be set to 1 when programming the CKGR_PLLAR register.
• DIVA: Divider A
• PLLACOUNT: PLLA Counter
Specifies the number of slow clock cycles before the LOCKA bit is set in PMC_SR after CKGR_PLLAR is written.
• OUTA: PLLA Clock Frequency Range
To optimize clock performance, this field must be programmed as specified in “PLL Characteristics” in the Electrical Char-
acteristics section of the product datasheet.
• MULA: PLLA Multiplier
0 = The PLLA is deactivated.
1 up to 254 = The PLLA Clock frequency is the PLLA input frequency multiplied by MULA+ 1.
6438F–ATARM–21-Jun-10
DIVA
0
1
2 - 255
31
23
15
–
7
OUTA
0xFFFFFC28
30
22
14
–
6
29
21
13
1
5
Divider Selected
Divider output is 0
Divider is bypassed
Divider output is the selected clock divided by DIVA.
28
20
12
–
4
MULA
DIVA
27
19
11
–
3
PLLACOUNT
26
18
10
–
2
AT91SAM9G45
25
17
–
9
1
24
16
–
8
0
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